Apparatus and method for virtualizing interrupts in a...

Electrical computers and digital data processing systems: input/ – Interrupt processing – Processor status

Reexamination Certificate

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C710S269000, C712S203000, C717S149000, C719S324000

Reexamination Certificate

active

07000051

ABSTRACT:
A resource and partition manager virtualizes interrupts without using any additional hardware in a way that does not disturb the interrupt processing model of operating systems running on a logical partition. In other words, the resource and partition manager supports virtual interrupts in a logically partitioned computer system that may include share processors with no changes to a logical partition's operating system. A set of virtual interrupt registers is created for each virtual processor in the system. The resource and partition manager uses the virtual interrupt registers to process interrupts for the corresponding virtual processor. In this manner, from the point of view of the operating system, the interrupt processing when the operating system is running in a logical partition that may contain shared processors and virtual interrupts is no different that the interrupt processing when the operating system is running in computer system that only contains dedicated processor partitions.

REFERENCES:
patent: 4400769 (1983-08-01), Kaneda et al.
patent: 4742447 (1988-05-01), Duvall et al.
patent: 5095427 (1992-03-01), Tanaka et al.
patent: 5187802 (1993-02-01), Inoue et al.
patent: 5325525 (1994-06-01), Shan et al.
patent: 5325526 (1994-06-01), Cameron et al.
patent: 5357632 (1994-10-01), Pian et al.
patent: 5361375 (1994-11-01), Ogi
patent: 5481747 (1996-01-01), Kametani
patent: 5504670 (1996-04-01), Barth et al.
patent: 5535321 (1996-07-01), Massaro et al.
patent: 5574914 (1996-11-01), Hancock et al.
patent: 5659786 (1997-08-01), George et al.
patent: 5692193 (1997-11-01), Jagannathan et al.
patent: 5694606 (1997-12-01), Pletcher et al.
patent: 5872963 (1999-02-01), Bitar et al.
patent: 5898855 (1999-04-01), Onodera et al.
patent: 5978830 (1999-11-01), Nakaya et al.
patent: RE36462 (1999-12-01), Chang et al.
patent: 6078970 (2000-06-01), Nordstrom et al.
patent: 6105050 (2000-08-01), Govindaraju et al.
patent: 6195676 (2001-02-01), Spix et al.
patent: 6199093 (2001-03-01), Yokoya
patent: 6247109 (2001-06-01), Kleinsorge et al.
patent: 6269391 (2001-07-01), Gillespie
patent: 6279046 (2001-08-01), Armstrong et al.
patent: 6381742 (2002-04-01), Forbes et al.
patent: 6418460 (2002-07-01), Bitar et al.
patent: 6487654 (2002-11-01), Dowling
patent: 6542926 (2003-04-01), Zalewski et al.
patent: 6587938 (2003-07-01), Eilert et al.
patent: 6598069 (2003-07-01), Rooney et al.
patent: 6615303 (2003-09-01), Endo et al.
patent: 6625638 (2003-09-01), Kubala et al.
patent: 6647508 (2003-11-01), Zalewski et al.
patent: 6711605 (2004-03-01), Sekiguchi et al.
patent: 6760783 (2004-07-01), Berry
patent: 6779065 (2004-08-01), Murty et al.
patent: 2001/0014905 (2001-08-01), Onodera
patent: 2002/0056076 (2002-05-01), Made
patent: 2003/0014466 (2003-01-01), Berger et al.
patent: 2003/0101440 (2003-05-01), Hardin et al.
patent: 2001188685 (2001-07-01), None
U.S. Appl. No. 09/838,057, “Method and Apparatus for Allocating Processor Resources in a Logically Partitioned Computer System,”, Armstrong et al., filed Apr. 19, 2001,
IBM Corporation, S/390 Processor Resource/Systems Manager Planning Guide (IBM Pub. No. GA22-7236-04, 5thEdition, Mar. 1999).
David L. Black, “Scheduling Support for Concurrency and Parallelism in the Mach Operating System,” Computer, IEEE Computer Society, vol. 23, No. 5, May 1, 1990.
T. L. Borden et al., “Multiple Operating Systems on One Processor Complex,” IBM Systems Journal, vol. 28, No. 1, 1989, pp. 104-122.
Menasce, D. et al. “Capacity Planning and Performance Modeling”, ISBN 0-13-035494-5, © 1994.
Leutenegger et al. “A Modeling Study of the TPC-C Benchmark”, Proceedings of the 1993 ACM SIGMOD Int'l Conference on Management of Data, 1993, pp. 22-31.
Levine, C. “Order-of-Magnitude Advantage on TPC-C Through Massive Parallelism”, Proceedings of the 1995 ACM SIGMOD Int'l Conference on Management of Data, 1995, pp. 464-465.
IBM Corporation, “AS/400 Logical Partitiond Hardware Planning Guide”, © 1999.
Schimunek, G. et al. “Slicing the AS/400 With Logical Partitioning: A How to Guide”, Aug. 1999.
IBM Corporation, “LPAR Configuration and Management”, First Edition, © Apr. 2002.
Bakshi et al., “Partitioning and Pieplining for Performance-Costrained Hardware/Software Systems,” 1999 IEEE, pp. 419-432.
Ayachi et al., “Hierarchical Processor Scheduling Policy for Multiprocessor Systems,” 1996 IEEE, pp. 100-109.
Marisa Gil et al., “The Enhancement of a User-level Thread Package Scheduling on Multiprocessors,” Sep. 1994, Euromicro Workshop on Parallel and Distributed Processing, pp. 228-236.
IBM AS/400e Logical Partitions: Learning About. © 1999, 2000. http://publib.boulder.ibm.com/pubs/html/as400/v4r5/ic2924/info/rzajx.pdf.
IBM AS/400e Logical Partitions: Planning for. © 1999, 2000. http://publib.boulder.ibm.com/pubs/html/as400/v4r5/ic2924/info/rzait.pdf.
IBM AS/400e Logical Partitions: Creating. © 1999, 2000. http://publib.boulder.ibm.com/pubs/html/as400/v4r5/ic2924/info/rzaj7.pdf.
IBM AS/400e Logical Partitions: Managing. © 1999, 2000. http://publib.boulder.ibm.com/pubs/html/as400/v4r5/ic2924/info/rzaj6.pdf.
IBM AS/400e Logical Partitions: Troubleshooting. © 1999, 2000. http://publib.boulder.ibm.com/pubs/html/as400/v4r5/ic2924/info/rzaj8.pdf.

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