Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-07-26
2002-10-08
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06463570
ABSTRACT:
TECHNICAL FIELD
The present invention relates in general to the fabrication of integrated circuit devices, and in particular to the verifying fabrication of salicide layers and other structural features in an integrated circuit device.
BACKGROUND INFORMATION
Metal oxide semiconductor transistors used in modem integrated circuit devices typically employ polysilicon gate electrodes. The conductivity of the polysilicon is increased by the formation of a metal salicide layer on the polysilicon. Typically, titanium (Ti) is used, forming a TiSi
2
salicide layer although other methods, for example, cobalt (Co) may also be used. (The deposition of the layer is typically done using a self-aligned salicidation process, and the resulting layer is typically referred to as a salicide layer or simply the salicide.)
Poor salicide formation during fabrication leads to reduced performance of the integrated circuit device. This may be particularly acute over the shallow trench isolation (STI) step. The STI step isolates the complementary active elements in the complementary metal oxide semiconductor (CMOS) devices. Poor salicide formation over the STI step can lead to short but high resistance paths. Furthermore, the formation of salicide can vary across the surface of the wafer whereby the formation of marginal salicide may be restricted to only a portion of the wafer surface. Existing test processes are not sensitive to this coverage variability. These typically employ a polysilicon serpentine deposited on a portion of the wafer between dies and measuring the resistance of the polysilicon. Consequently, there is a need in the art for apparatus and methods to characterize salicide layers in CMOS integrated circuit devices, and in particular methods and apparatus which permit characterization at the die level.
SUMMARY OF THE INVENTION
The aforementioned needs are addressed by the present invention. Accordingly there is provided, in a first form, a process step verification method. The method includes providing a ring oscillator on each die being verified, the ring oscillator having a structure adapted for sensitizing the ring oscillator to a predetermined process step. A period of the ring oscillator for the die under test is measured and compared with a preselected specification.
There is also provided, in a second form, a data processing system for process step verification. The system includes circuitry operable for measuring a period of a ring oscillator for a die under test, in which the ring oscillator is provided on each die being verified. Each ring oscillator has a structure adapted for sensitizing the ring oscillator to a predetermined process step. The system also contains circuitry operable for comparing the period with a preselected specification.
Additionally there is provided, in a third form, a computer program product embodied in a storage medium. The program product for process step verification constitutes a program of instructions for performing the steps of a method which includes measuring a period of a ring oscillator for a die under test, in which the ring oscillator is provided on each die being verified. The ring oscillator has a structure adapted for sensitizing the ring oscillator to a predetermined process step. The method also includes comparing the period with a preselected specification.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.
REFERENCES:
patent: 5045811 (1991-09-01), Lewis
patent: 5095267 (1992-03-01), Merrill et al.
patent: 5204559 (1993-04-01), Deyhimy et al.
patent: 5373535 (1994-12-01), Ellis et al.
patent: 5440592 (1995-08-01), Ellis et al.
patent: 5459766 (1995-10-01), Huizer et al.
patent: 5606292 (1997-02-01), Oh
patent: 5796313 (1998-08-01), Eitan
patent: 5811983 (1998-09-01), Lundberg
patent: 5854576 (1998-12-01), Swan
patent: 5923676 (1999-07-01), Sunter et al.
patent: 5940725 (1999-08-01), Hunter et al.
patent: 5956289 (1999-09-01), Norman et al.
patent: 6047248 (2000-04-01), Georgiou et al.
patent: 6069849 (2000-05-01), Kingsley et al.
patent: 6087234 (2000-07-01), Wu
patent: 6121810 (2000-09-01), Philpott
patent: 6160755 (2000-12-01), Norman et al.
patent: 6204694 (2001-03-01), Sunter et al.
patent: 6211727 (2001-04-01), Carobolante
patent: 6229402 (2001-05-01), Katoaka et al.
patent: 6300785 (2001-10-01), Cook et al.
Dunn Michael J.
Fuselier Mark Brandon
Advanced Micro Devices
Dinh Paul
Newberger Barry S.
Winstead Sechrest & Minnick P.C.
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