Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
1999-06-28
2001-01-30
Nelms, David (Department: 2818)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C365S154000
Reexamination Certificate
active
06181161
ABSTRACT:
BRIEF DESCRIPTION OF THE INVENTION
This invention relates generally to field programmable logic devices. More particularly, this invention relates to an improved technique for programming and verifying macrocell based field programmable logic devices.
BACKGROUND OF THE INVENTION
FIG. 1
illustrates a prior art programming and verification scheme used in field programmable logic devices. In a typical embodiment of
FIG. 1
Array Data Shift Register (ADSR) Select Circuit
122
is programmed to select individual flip-flops
102
A-
102
N in ADSR
104
. Once selected, individual flip-flops
102
A-
102
N are enabled and can accept programming in the form of data or sequential instructions. Each flip-flop
102
A-
102
N contains at least one programmable bit. The programmable bit is programmed when data is input to the D-input of selected flip-flop(s)
102
A-
102
N. The programmable bits, taken together, can define at least one programmable address in ADSR
104
. After data is input to flip-flops
102
A-
102
N, control for the program is transferred from ADSR
104
to Product-Term Logic Gates
112
A-
112
N. Program Mode Controller
127
sets the Product-Term Logic Gates' second input to a logical “1” while the circuit is being programmed. (This second input is used as a data line after the circuit is programmed and while it is being used by a user.) These programming operations must be carried out in a serial fashion, completely loading the data into one of the selected flip-flops before loading the next. Also, the structural limitations associated with prior art macrocell devices, such as that shown and described in
FIG. 1
, are such that in order to expand the circuit's capability a typical prior art circuit may have a mirrored (or second identical) macrocell also using MSR
126
. In such a case, programming and verification steps take twice as long because the same operation must be serially processed through MSR. This serial limitation occurs because all of the data entered into any system component must be combined in Gate
124
, then processed through Macrocell Scan Register (MSR)
126
, and MSR
126
accepts only one piece of data at a time.
Once the programming operation is complete, in the usual case a verification operation is performed. Level Tester
106
performs the verification operation by performing a Margin High and a Margin Low test on signals from MSR
126
. Margin High and Margin Low operations are stress tests designed to test a line or address at its upper and lower extremes. One skilled in the art would be familiar with suitable methods of level testing, including but not limited to using shift registers.
The problem with this prior art approach is that all programming operations must be executed in a serial fashion because the processing is executed through MSR
126
. In addition to the increased time required by serial processing, this type of processing requires a relatively large number of test vectors. These factors can result in large memory load times when a device is being tested with automatic test equipment. The large number of test vectors is especially problematic in the case of in-system programming of embedded controllers. That is, to support in-system programming, a relatively large amount of memory is required to store the vectors associated with the verification process.
In view of the foregoing, it would be highly desirable to provide an improved verification scheme for macrocell based architectures in field programmable logic devices. Ideally, the scheme would reduce the number of required vectors and eliminate the need for an MSR. As a result, in-system programming via an embedded controller could be performed with reduced memory requirements. In addition, test time associated with automatic test equipment would be reduced.
SUMMARY OF THE INVENTION
A method of programming and verifying a macroscale based architecture in a field programmable logic device includes the step of selecting a flip-flop. The flip-flop contains a programmable bit that accepts data. A Switch Controller then selectably enables either one of two banks of switches. If the first bank of switches is selected, the programming operation is selected. If the second bank of switches is enabled, the verification operation is selected. The verifying operation includes the step of automatically incrementing a base address through a set of incremented addresses. For each incremented address produced by the incrementing step, a margin low operation is performed with a Level Tester and a margin high operation is performed with the Level Tester. Thus, unlike the prior art, margin operations with the present invention are performed without using a macrocell scan register. Advantageously, processing is improved because relatively large groups of data are loaded into flip-flops in the ADSR. And, these large data groups can be processed at the same time, rather than in a serial fashion as in the prior art.
The invention provides a programming and verification scheme for macrocell based architectures in field programmable logic devices. The invention reduces the number of vectors that are processed during verification. As a result, in-system programming via an embedded controller is performed with reduced memory requirements. Also, this invention eliminates the need for an output shift register. Further, testing time associated with automatic test equipment is reduced.
REFERENCES:
patent: 5761460 (1998-06-01), Santos et al.
Ishihara Brad
Nishiwaki Kunio
Rangasayee Krishna
Altera Corporation
Nelms David
Pennie & Edmonds LLP
Tran M
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