Apparatus and method for verifying layout interconnections...

Details Apparatus and method for verifying layout interconnections... Apparatus and method for verifying layout interconnections...

2008-01-08

2008-01-08

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000, C703S002000

Reexamination Certificate

active

07318207

ABSTRACT:
A method for verifying layout interconnections includes extracting a loop circuit as a loop portion in a first circuit model. The first circuit model includes first branch interconnections included in the loop portion and second branch interconnections, first nodes, and terminals of circuit elements. The loop portion is replaced with a second node to generate a second circuit model which does not have a loop portion, based on the first circuit model. A second current value of each of the second branch interconnections is calculated, based on the second circuit model. A third circuit model of the loop portion is generated, based on the first interconnections. A first current value of each of the first branch interconnections is calculated, based on the third circuit model. The first and second current value are compared with a predetermined current value to carry out verification.

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Potash et al., Application of Unilateral and graph techniques to analysis of linear circuit, 1968, ACM, pp. 367-378.

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