Apparatus and method for utilizing partially defective memory de

Details Apparatus and method for utilizing partially defective memory de Apparatus and method for utilizing partially defective memory de

1980-09-30

1982-10-19

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Bad bit

365230, G11C 1300

Patent

active

043553761

ABSTRACT:
An apparatus and method of utilizing a group of partially defective memory devices in conjunction with a single faultfree memory device to form an effectively faultfree memory unit. Each of the partial devices and the faultfree device are characterized as requiring an address input to be presented in two segments at separate times during an access cycle. Each of the partial devices is characterized as having all of its respective faults within a contiguous address space, the group of partial devices configured to form one continuous addressable storage area. The first segment of the input address is presented to the group of partial devices and the faultfree device, and then a first stage access is initiated to all devices. Concurrently, the second segment of the input address is compared with the address combination which defines the faulty areas of the partial devices being accessed. If a match is obtained, the second segment of the input address is modified to specify an address in a portion of the faultfree device allocated for the corresponding partial device, and a second stage access is initiated to the faultfree device. If a match is not obtained, a second stage access is initiated to the group of partial devices utilizing the second segment of the unmodified input address.

REFERENCES:
patent: 4047163 (1977-09-01), Choate
patent: 4310901 (1982-01-01), Harding et al.

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