Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1996-05-13
1998-05-19
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Bad bit
36523004, G11C 1300
Patent
active
057544840
ABSTRACT:
An apparatus (101, 110) and method provide for memory utilization and management which may expand the number of write operations for limited write memories, such as non-volatile memory, to provide for more optimal performance of systems such as computer or communication systems. Such memory utilization, in accordance with the present invention, includes allocating portions of the limited write memory, as a memory structure, for an ordinal or parameter designation. Upon system initialization or start up, comparison of adjacent ordinal designations may then be utilized to precisely locate the area of memory into which data or other information was previously written, indicating the current memory locations for current read operations, and to precisely locate the area of memory into which data or other information is to be written next, in order to provide the proper memory location for a subsequent write operation. The ordinal designation also provides for tracking the number of write operations performed in a given memory location, to prevent overuse of a given memory location and concomitant potential loss of data. In the preferred embodiment, the apparatus includes a processor (150) and memory (155), which includes a working memory and a limited write memory.
REFERENCES:
patent: 4862421 (1989-08-01), Tran
Fears Terrell W.
Gamburd Nancy R.
Klayman Jeffrey T.
Motorola Inc.
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