Electrical computers and digital processing systems: processing – Processing control – Arithmetic operation instruction processing
Reexamination Certificate
1999-03-08
2001-06-12
Chan, Eddie (Department: 2783)
Electrical computers and digital processing systems: processing
Processing control
Arithmetic operation instruction processing
C712S224000, C712S228000, C712S235000, C712S239000, C708S525000
Reexamination Certificate
active
06247117
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the field of microprocessors and, more particularly, to floating-point execution units within microprocessors.
2. Description of the Related Art
Microprocessors are typically designed with a number of “execution units” that are each optimized to perform a particular set of functions or instructions. For example, one or more execution units within a microprocessor may be optimized to perform memory accesses, i.e., load and store operations. Other execution units may be optimized to perform general arithmetic and logic functions, e.g., shifts and compares. Many microprocessors also have specialized execution units configured to perform more complex floating-point arithmetic operations including multiplication and reciprocal operations. These specialized execution units typically comprise hardware that is optimized to perform one or more floating-point arithmetic functions.
Most microprocessors must support multiple data types. For example, x86 compatible microprocessors must execute instructions that are defined to operate upon an integer data type and instructions that are defined to operate upon floating-point data types. Floating-point data can represent numbers within a much larger range than integer data. For example, a 32-bit signed integer can represent the integers between −2
31
and 2
31
−1 (using two's complement format). In contrast, a 32-bit (“single precision”) floating-point number as defined by the Institute of Electrical and Electronic Engineers (IEEE) Standard 754 has a range (in normalized format) from 2
−126
to 2
127
×(2−2
−23
) in both positive and negative numbers.
Turning now to
FIG. 1A
, an exemplary format for an 8-bit integer
100
is shown. As illustrated in the figure, negative integers are represented using the two's complement format
104
. To negate an integer, all bits are inverted to obtain the one's complement format
102
. A constant of one is then added to the least significant bit (LSB).
Turning now to
FIG. 1B
, an exemplary format for a 32-bit (single precision) floating-point number is shown. A floating-point number is represented by a significand, an exponent and a sign bit. The base for the floating-point number is raised to the power of the exponent and multiplied by the significand to arrive at the number represented. In microprocessors, base
2
is typically used. The significand comprises a number of bits used to represent the most significant digits of the number. Typically, the significand comprises one bit to the left of the radix point and the remaining bits to the right of the radix point. In order to save space, the bit to the left of the radix point, known as the integer bit, is not explicitly stored. Instead, it is implied in the format of the number. Additional information regarding floating-point numbers and operations performed thereon may be obtained in IEEE Standard 754 (IEEE-754). Unlike the integer representation, two's complement format is not typically used in the floating-point representation. Instead, sign and magnitude form are used. Thus, only the sign bit is changed when converting from a positive value
106
to a negative value
108
.
Numerical data formats, such as the IEEE-754, often include a number of special and exceptional cases. These special and exceptional cases may appear in one or more operands or one or more results for a particular instruction.
FIG. 2
illustrates the sign, exponent, and significand formats of special and exceptional cases that are included in the IEEE-754 floating-point standard. The special and exceptional cases shown in
FIG. 2
include a zero value, an infinity value, NaN (not-a-number) values, and a denormal value. An ‘x’ in
FIG. 2
represents a value that can be either one or zero. NaN values may include a QNaN (quiet not-a-number) value and a SNaN (signaling not-a-number) value as defined by a particular architecture. The numbers depicted in
FIG. 2
are shown in base
2
format as indicated by the subscript
2
following each number. As shown, a number with all zeros in its exponent and significand represents a zero value in the IEEE-754 floating-point standard. A number with all ones in its exponent, a one in the most significant bit of its significand, and zeros in the remaining bits of its significant represents an infinity value. The remaining special and exceptional cases are depicted similarly.
In order to conform to a particular numerical format, a microprocessor must be configured to detect and handle the special and exceptional cases for that format. Detecting and handling special and exceptional cases, however, generally requires additional microprocessor resources and produces undesirable execution latencies. Latencies may occur both when a microprocessor examines the operand or operands of an instruction and when it examines the result or results of an instruction. It would be desirable to reduce the latencies required to detect and handle special and exceptional cases for a numerical format. It would also be desirable to minimize and optimize the microprocessor resources required to detect and handle special and exceptional cases.
SUMMARY
The problems outlined above are in large part solved by the use of checking instructions in accordance with the present invention. Generally speaking, a checking instruction is included in the microcode of floating-point instructions to detect special and exceptional cases of a defined data format. A checking instruction is configured to set one or more flags in a flags register if it detects a special or exceptional case for an operand value. A checking instruction may also be configured to set the result or results of a floating-point instruction to a result value. In addition, a checking instruction may be configured to set one or more bits in a status register if a special or exceptional case is detected. After a checking instruction completes execution, a subsequent microcode instruction can be executed to determine if one or more flags were set by the checking instruction. If one or more flags have been set by the checking instruction, the subsequent microcode instruction can branch to a non-sequential microcode instruction to handle the special or exceptional case detected by the checking instruction.
The use of checking instructions in accordance with the present invention may allow a floating-point execution unit to detect special and exceptional cases of a defined data format in an advantageous manner. Checking instructions may simplify the microcode for microcoded floating-point instructions. By simplifying the microcode, the amount of microcode ROM space required to store the microcode may be reduced. Further, a single checking instruction may minimize the instruction latency associated with the detection of special and exceptional cases. Checking instructions may also remove the need to take a microarchitectural trap if a special or exceptional case is detected. In addition, the use of checking instructions may allow for a simplification of the hardware needed to detect special and exceptional cases. Furthermore, checking instructions may reduce the amount of constant ROM storage required to hold the possible results of special and exceptional cases.
Broadly speaking, an apparatus that includes a flag register and a first execution unit is contemplated. The first execution unit is configured to execute a plurality of microinstructions that correspond to a floating-point instruction. The plurality of microinstructions includes a checking instruction that is configured to determine whether an operand value of an operand specified by the floating-point instruction corresponds to a special or exceptional case of a defined data format. The checking instruction is also configured to signal the flag register to set one or more flags if the operand value corresponds to a special or exceptional case of the defined data format
A method for executing instructions in a microproc
Advanced Micro Devices , Inc.
Chan Eddie
Conley Rose & Tayon PC
Kivlin B. Noäl
Patel Gautam R.
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