Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-07-17
2007-07-17
Do, Thuan (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C703S014000
Reexamination Certificate
active
11248709
ABSTRACT:
In one embodiment of the invention, a method for unified debug for simulation, includes: generating a transaction from a hardware verification language (HVL) testbench; copying signal states in the HVL testbench after the transaction is generated, wherein the signal states are copied in a hardware description language (HDL) mirror; generating a response to the transaction from a device-under-test (DUT); and displaying the signal states in the HVL testbench on a display screen as a first waveform, and displaying the DUT response on the display screen as a second waveform. In another embodiment of the invention, an apparatus is provided for unified debug for simulation, where the apparatus can perform the above method.
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Do Thuan
Hewlett--Packard Development Company, L.P.
Lange Ricahrd P.
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