Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2001-07-30
2003-11-18
Verbrugge, Kevin (Department: 2188)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S103000
Reexamination Certificate
active
06651155
ABSTRACT:
BRIEF DESCRIPTION OF THE INVENTION
This invention relates generally to techniques for configuring programmable logic devices. More particularly, this invention relates to a technique for configuring a programmable logic device using a hardware circuit to translate a programmer object file.
BACKGROUND OF THE INVENTION
A programmable logic device or PLD (sometimes referred to as a PAL, PLA, FPLA, EPLD, EEPLD, LCA, or FPGA) allows a user to electrically program standard, off-the-shelf logic elements to meet a user's specific needs. PLDs are currently represented by, for example, Altera's MAX® series of PLDs and FLEX® series of PLDs.
A programmable logic device is configurable circuitry that is programmed by a process commonly referred to as device configuration. During configuration, user-defined data is converted to binary representations, or configuration bits, to implement either logic, interconnect or memory functions. A PLD has a number of relatively simple logic modules which can be interconnected in any of a wide variety of ways via a general purpose interconnection network to enable the circuit to perform logic functions which can be quite complex.
A typical PLD consists of an array of identical logic cells that can be individually programmed, and which can be arbitrarily interconnected to each other to provide internal input and output signals, thus permitting the performance of highly complex combinational and sequential logic functions. During configuration, a program is implemented in the PLD by setting the device routing and the states of programmable elements, such as configuration memory cells. The configuration memory cells are loaded with configuration data selected to cause the PLD to perform a desired function. For some PLDs, reprogramming is achieved by changing the configuration data contained in the memory cells.
A PLD architecture is commonly characterized by the logic structure of its family of programmable integrated circuits. Architecture design parameters typically include device density, speed, functionality, and other design, processing and performance considerations. As PLD architectures and chip designs continue to evolve based on improvements involving such considerations, the task of programming the circuit tends to become more complex.
As the number of elements increases, it becomes important to improve the techniques used to interconnect them. For example, it is important to provide enough interconnection pathways between the programmable logic elements so that the capabilities of those elements can be fully utilized and so that complex logic functions (requiring concatenation of programmable logic elements) can be performed, without providing so many pathways that there is wasteful excess of this type of resource. Similarly, as the number of programmable elements increases, the complexity of the logic which can be performed also increases. But improvements in density, speed and the other design considerations noted above tend to increase the complexity of the task of programming the circuit.
Configuration data is a bit stream of programming information made up of configuration bits. The configuration data is in a binary format stored as a configuration file, also frequently referred to as a Programmer Object File (POF). Upon start-up of a system, configuration data from a configuration memory is downloaded into a programmable logic device. Some PLD architectures use SRAM configuration elements that require configuration data to be loaded every time the circuit device powers up. Before configuration, some devices initiate a Power-On Reset (POR). This POR event clears the device and prepares it for configuration. While the POR time is very fast, some devices impose an additional delay that allows system power to stabilize before configuration. Once the configuration data is downloaded into the PLD, the PLD executes the logic functions specified by the POF.
During initialization, which generally occurs immediately after configuration, the PLD device resets registers, enables I/O pins, and begins to operate as a logic device. For devices where configuration and initialization occur, these processes together are often referred to as the command mode and normal device operation is the user mode.
In some configurations and devices, elements are configured in-circuit by loading new configuration data into the device. Real-time reconfiguration can be performed by forcing the device into command mode with a device pin, loading different configuration data, re-initializing the device, and resuming user-mode operation. In many cases the reconfiguration process requires less than 40-300 ms and can be used to reconfigure an entire system dynamically. In-field upgrades can be performed by distributing new configuration files by modem, over the internet, by diskette or other communication methods.
Currently, new configuration data is required every time the architecture of a programmable logic device is altered. It is relatively time consuming to produce new configuration data, particularly given the variety of device architectures and approaches used for configuration purposes. Accordingly, it would be highly desirable to be able to utilize existing configuration data with evolving programmable logic device architectures.
SUMMARY OF THE INVENTION
The invention includes a circuit for translating a configuration file used to configure a programmable logic device. The circuit includes a first register to serially receive configuration data. A second register receives, in parallel, configuration data from the first register. A translation address memory translates an original address for a selected configuration bit of the configuration data to a translated address. A translation memory stores the selected configuration bit at the translated address. Control logic selectively downloads configuration data from the translation memory to a programmable logic device core.
The invention also includes a method of translating a configuration file used to configure a programmable logic device. The method includes the step of shifting configuration data into a first register. The configuration data is loaded in parallel from the first register into a second register. Additional configuration data is shifted into the first register while performing the steps of obtaining a new address for a selected configuration bit in the second register, writing the selected configuration bit to the new address in a memory, and repeating the obtaining and writing steps until all configuration bits in the second register have been processed. The contents of the memory are then downloaded to a programmable logic device core so as to configure the programmable logic device.
REFERENCES:
patent: 5590305 (1996-12-01), Terrill et al.
patent: 6052755 (2000-04-01), Terrill et al.
patent: 6314550 (2001-11-01), Wang et al.
patent: 6414871 (2002-07-01), Wirtz et al.
Bocchino Vincent T.
Cauneau Stephane
Hendry Colin
Patel Virendra
Altera Corporation
Verbrugge Kevin
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