Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2005-03-08
2005-03-08
Myers, Paul R. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S308000, C710S310000, C710S022000, C710S027000, C710S052000, C710S057000, C711S154000
Reexamination Certificate
active
06865638
ABSTRACT:
An apparatus and method for transferring multi-byte words having arbitrary start and end byte addresses are described. Data transfers between a memory and a PCI-bus pass through a PCI-side aligner unit, PCI FIFO, Endian swap logic, and PCI-bus interface unit under the control of a PCI FIFO controller. The PCI-side aligner unit properly aligns the data while communicating data with the memory's bus on a word-at-a-time basis, and communicating data with the PCI FIFO managed on a byte-at-a-time basis synchronous with a clock signal provided by the memory's bus. The Endian swap logic properly orients the data in big or little Endian orientation. The PCI-bus interface unit communicates data with the PCI-bus on a word-at-a-time basis, and communicates data with the PCI FIFO managed on a byte-at-a-time basis synchronous with a clock signal provided by the PCI-bus. To keep track of unread stored data in the PCI FIFO, the PCI FIFO controller includes a #Bytes logic unit that automatically accounts for wrap-around of write and read pointers for the PCI FIFO.
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Integrated Device Technology Inc.
Myers Paul R.
Okumoto Victor H.
Phan Raymond N
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