Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
1998-12-29
2001-05-22
Yoo, Do (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S171000, C711S172000, C711S202000, C710S066000, C710S120000
Reexamination Certificate
active
06237069
ABSTRACT:
BRIEF DESCRIPTION OF THE INVENTION
The present invention relates generally to digital circuit interfaces. More particularly, the present invention relates to an apparatus and method for transferring data between a memory in a processor having a first word width and a dynamic random access memory (DRAM) having a second, narrower word width.
BACKGROUND OF THE INVENTION
FIG. 1
is a diagrammatic view of a conventional digital system
100
including a processor
110
and a memory device
115
. The processor
110
, such as a digital signal processor (DSP), includes a processor memory
111
comprising a plurality of words having a first word width. The memory device
115
, such as a dynamic random access memory (DRAM), comprises a plurality of words having a second word width. Data is transferred between the processor memory
111
and the memory device
115
under the control of the processor
110
via a data bus
116
. In many digital systems, the processor memory
111
and the memory device
115
have different word widths such that for data to be transferred between the two memories, the data must first be converted from one word width to the other. In the digital system
100
illustrated in the figure, the processor memory
111
has a 24-bit word width while the memory device
115
has a narrower 16-bit word width.
FIG. 2
illustrates the problem of transferring data between the processor memory
111
and the memory device
115
for data in a digital multichannel (e.g., stereo) format. In this example, data is transferred between the processor memory
111
and the memory device
115
in 96-bit blocks. Because the word widths of the processor memory and the memory device are different, a block of data is stored in a first, unpacked format in the processor memory and in a second, packed format in the memory device to conserve space. Therefore, when transferring a block of data between the processor memory
111
and the memory device
115
, the data must be converted from the unpacked format to the packed format or vice versa. Unfortunately, in the prior art, this conversion process degrades system performance by increasing the latency and/or decreasing the throughput of the block transfer.
In view of the shortcomings of prior art methods for data transfer, it is an object of the present invention to provide an apparatus and method for transferring data between memories having different word widths that provides a low latency and a high throughput.
SUMMARY OF THE INVENTION
The present invention is an apparatus and method for transferring a block of data between a first storage area in a first, unpacked format and a second storage area in a second, packed format. The first format consists of a plurality of w
1
-bit wide words while the second format consists of a plurality of w
2
-bit wide words, where w
1
>w
2
. The first and second storage areas may comprise first and second memories having word widths of w
1
bits and W
2
bits, respectively. The apparatus of the present invention includes: (1) a plurality of working registers, each working register having a word width of at least w
2
bits, (2) a data routing circuit coupled to the first storage area, the second storage area and the working registers to route the block of data therebetween and (3) a control circuit coupled to the first storage area, the second storage area, the working registers and the data routing circuit to control the transfer of the block of data between the first and second storage areas. When transferring the block of data from the first storage area to the second storage area, the data routing circuit and the control circuit are jointly configured to: (1) concurrently transfer a first portion of a first word from the first storage area to a first location in the second storage area and a second portion of the first word from the first storage area to a first working register and (2) transfer both a portion of a second word from the first storage area and the contents of a portion of the first working register to a second location in the second storage area. When transferring the block of data from the second storage area to the first storage area, the data routing circuit and the control circuit are jointly configured to transfer the contents of both a second working register and a portion of a third working register to a location in the first storage area.
The method of the present invention includes two embodiments: a first embodiment for transferring a block of data from the first storage area in the first format to the second storage area in the second format and a second embodiment for transferring a block of data from the second storage area in the second format to the first storage area in the first format. The first embodiment of the method includes at least the following steps: (1) transferring a first portion of a first word from the first storage area to a first location in the second storage area, (2) concurrently transporting a second portion of the first word from the first storage area to a first working register and (3) moving both a first portion of a third word from the first storage area and the contents of a portion of the first working register to a third location in the second storage area. The second embodiment of the method includes at least the following steps: (1) transferring a first word from the second storage area to a first working register, (2) transporting a third word from the second storage area to a third working register and (3) moving the contents of both the first working register and a first portion of the third working register to a first location in the first storage area.
The apparatus and method of the present invention transfers blocks of data between the first and second storage areas with a low latency and a high throughput. The present invention achieves this by using the set of working registers to temporarily store and manipulate portions of the blocks of data as they are being transferred between the first and second storage areas.
REFERENCES:
patent: 5768546 (1998-06-01), Kwon
Oak Technology, Inc.
Pennie & Edmonds LLP
Yoo Do
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