Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2000-12-07
2002-11-19
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S202000, C711S206000, C711S208000, C711S212000
Reexamination Certificate
active
06484249
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus and method for transferring data between address spaces having different structures, as well as to a computer-readable medium storing a computer program therefor. More particularly, the present invention relates to an apparatus and method for transferring data in such an environment where the source and destination address spaces are organized by a plurality of various-sized segments. The invention also relates to a computer-readable medium storing a data transfer program which causes a computer to function as the above apparatus.
2. Description of the Related Art
When transferring data between differently structured address spaces (e.g., computer main memory, input and output channels, external mass storage), it is necessary to properly associate a given source area with its corresponding destination area. To this end, computer systems generally use an address translation table to map one address space to another.
FIG. 11
illustrates a conventional address mapping method. In this example, an address translation table
103
describes how to associate a p-bit wide address space
101
with a q-bit wide address space
102
. The two address spaces
101
and
102
are each divided into a plurality of segments with a size of a
1
. These segments constituting the address spaces
101
and
102
are designated by their respective index numbers “1-0” to “1-n” and “2-0” to “2-n.” The address translation table
103
contains a plurality of table entries
103
a
, which describe how to translate addresses within each segment of the size a
1
. These table entries have their index numbers “3-0” to “3-n,” similarly to the address spaces
101
and
102
.
Each entry of the address translation table
103
is associated with a particular segment of the address space
102
, permitting a given segment in the address space
101
to be mapped to its corresponding part of the address space
102
. Take the table entry
103
a
of index “3-j,” for example. Besides storing the index value i of the segment
101
a
, this table entry
103
a
is associated with a segment
102
a
of index “2-j” in the address space
102
. This setup of the table entry
103
a
enables the segments
101
a
to be mapped to the segment
102
a.
The conventional address mapping method is, however, not efficient enough because of its lack of flexibility in handling uneven segment sizes. As previously stated, the conventional method only supports a single segment type. Although the data to be transferred may actually include some blocks that are larger than others, the conventional method cannot handle them as a bulk segment, because the step size of address translation is not allowed to exceed the greatest common divisor of such different block sizes.
Suppose, for example, that the source address space has two portions with different segment sizes a
1
and (a
1
xs), where s is an integer, and data is to be transferred from these two portions to another address space. In this situation, the translation step size of the address translation table must be chosen from among the common divisors of a
1
and (a
1
xs). That is, the translation step size cannot exceed a
1
, the greatest common divisor of the two segment sizes. Since a mapping occurs at every segment of the size a
1
, the related hardware and software mechanisms are triggered s times as frequently as in the case where the segment size is (a
1
xs), being unable to enjoying the advantage of the large source data blocks.
SUMMARY OF THE INVENTION
Taking the above into consideration, an object of the present invention is to provide an apparatus which efficiently transfers a plurality of data segments with different sizes.
It is another object of the present invention to provide a method which efficiently transfers a plurality of data segments with different sizes.
To accomplish the first object, according to the present invention, there is provided a data transfer apparatus which transfers data from a first address space to a second address space, where the first and second address spaces are different in data structure. This data transfer apparatus comprises the following elements: an address translation table storage unit, a base address register, a boundary location register, a translation step size register, a translation descriptor domain selector, and a data segment association unit.
The address translation table storage unit stores an address translation table which is organized by a plurality of translation descriptor domains to support a plurality of translation step sizes. The base address register stores base addresses of a plurality of portions of the second address space which are corresponding to the plurality of translation descriptor domains. The boundary location register stores the boundary location of each translation descriptor domain. The translation step size register stores the translation step size that is supported in each translation descriptor domain. The translation descriptor domain selector selects one of the translation descriptor domains that is suitable for mapping a given data segment in the first address space. The data segment association unit associates that data segment in the first address space with another data segment in the second address space, according to the translation step size supported in the translation descriptor domain selected by the translation descriptor domain selector.
To accomplish the second object, according to the present invention, there is provided a method of transferring data from a first address space to a second address space, where the first and second address spaces are different in data structure. This method comprising the following steps: (a) storing an address translation table which is organized by a plurality of translation descriptor domains to support a plurality of translation step sizes; (b) storing base addresses of a plurality of portions of the second address space which are corresponding to the plurality of translation descriptor domains; (c) storing boundary locations of the plurality of translation descriptor domains; (d) storing translation step sizes that are respectively supported in the plurality of translation descriptor domains; (e) selecting one of the translation descriptor domains that is suitable for mapping a data segment in the first address space; and (f) associating the data segment in the first address space with another data segment in the second address space, according to the translation step size supported in the selected translation descriptor domain.
The above and other objects, features and advantages of the present invention will become apparent from the following description when taken in conjunction with the accompanying drawings which illustrate preferred embodiments of the present invention by way of example.
REFERENCES:
patent: 4835734 (1989-05-01), Kodaira et al.
patent: 5649142 (1997-07-01), Lavelle et al.
patent: 5802605 (1998-09-01), Alpert et al.
patent: 603 994 (1994-06-01), None
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patent: 2 008 822 (1979-06-01), None
Hirai Koichi
Kai Toshihiko
Fujitsu Limited
Greer Burns & Crain Ltd
Moazzami Nasser
Yoo Do Hyun
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