Electrical computers and digital data processing systems: input/ – Intrasystem connection – System configuring
Reexamination Certificate
2006-04-04
2006-04-04
Auve, Glenn A. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
System configuring
C711S170000, C326S030000, C365S189011
Reexamination Certificate
active
07024502
ABSTRACT:
A memory system includes a memory module having a plurality of memory devices and a supplemental memory device that stores information pertaining to the plurality of memory devices. The memory module also includes an integrated circuit device having controller circuitry that communicates with the plurality memory of devices, the integrated circuit device including a receiver circuit to sample receive data from an external signal line at a sample time, and a first register to store a first value representative of a sampling time adjustment that is applied to the sample time. The first value is determined based on the information pertaining to the plurality of memory devices.
REFERENCES:
patent: 4627080 (1986-12-01), Debus, Jr.
patent: 5029272 (1991-07-01), Fourcroy et al.
patent: 5228064 (1993-07-01), Viviano
patent: 5596285 (1997-01-01), Marbot et al.
patent: 5684421 (1997-11-01), Chapman et al.
patent: 5778419 (1998-07-01), Hansen et al.
patent: 5831929 (1998-11-01), Manning
patent: 5838177 (1998-11-01), Keeth
patent: 5852378 (1998-12-01), Keeth
patent: 5860080 (1999-01-01), James et al.
patent: 5870347 (1999-02-01), Keeth et al.
patent: 5872736 (1999-02-01), Keeth
patent: 5892981 (1999-04-01), Wiggers
patent: 5910920 (1999-06-01), Keeth
patent: 5920518 (1999-07-01), Harrison et al.
patent: 5926034 (1999-07-01), Seyyedy
patent: 5926651 (1999-07-01), Johnston et al.
patent: 5935263 (1999-08-01), Keeth et al.
patent: 5940608 (1999-08-01), Manning
patent: 5940609 (1999-08-01), Harrison
patent: 5946244 (1999-08-01), Manning
patent: 5946260 (1999-08-01), Manning
patent: 5949254 (1999-09-01), Keeth
patent: 5959481 (1999-09-01), Donnelly et al.
patent: 5959929 (1999-09-01), Cowles et al.
patent: 5963502 (1999-10-01), Watanabe et al.
patent: 5986955 (1999-11-01), Siek et al.
patent: 5996043 (1999-11-01), Manning
patent: 6000022 (1999-12-01), Manning
patent: 6011732 (2000-01-01), Harrison et al.
patent: 6014759 (2000-01-01), Manning
patent: 6016282 (2000-01-01), Keeth
patent: 6026050 (2000-02-01), Baker et al.
patent: 6026051 (2000-02-01), Keeth et al.
patent: 6028451 (2000-02-01), Ruff
patent: 6029250 (2000-02-01), Keeth
patent: 6029252 (2000-02-01), Manning
patent: 6031787 (2000-02-01), Jeddeloh
patent: 6032220 (2000-02-01), Martin et al.
patent: 6032274 (2000-02-01), Manning
patent: 6034878 (2000-03-01), Osaka et al.
patent: 6047346 (2000-04-01), Lau et al.
patent: 6154821 (2000-11-01), Barth et al.
patent: 6321282 (2001-11-01), Horowitz et al.
patent: 6442644 (2002-08-01), Gustavson et al.
patent: 6448813 (2002-09-01), Garlepp et al.
patent: 6449727 (2002-09-01), Toda
patent: 6462588 (2002-10-01), Lau et al.
patent: 6463392 (2002-10-01), Nygaard et al.
patent: 6516365 (2003-02-01), Horowitz et al.
patent: 6661268 (2003-12-01), Stark et al.
patent: 6684263 (2004-01-01), Horowitz et al.
Gabara, Thaddeus J., “Digitally Adjustable Resistors in CMOS for High-Performance Applications”,IEEE J. Solid-State Circuits, vol. 27, No. 8, Aug. 1992.
Dally and Poulton, “Digital Systems Engineering”, TOC, pp. 361-366 (1998).
Intel, “82243BX Host Bridge Datasheet”, pp. 2-4, 3-25 to 3-27, 4-19 to 4-20.
Intel, “Intel® 440BX AGPset: 82443BX Host Bridge/Controller:Datasheet”, TOC: pp. 1-1 to 5-9 (1998).
Poulton, “Signaling in High-Performance Memory Systems”,ISSCC, 1-59 (1999).
Song and Soo, “NRZ Timing Recovery Technique for Band-Limited Channels”,IEEE Journal of Solid-State Circuits, 32(4):514-520 (1997).
Gillingham, Peter, “SLDRAM Architectural and Functional Overview”, SLDRAM Consortium, pp. 1-14, Aug. 29, 1997.
Intel Corporation, “Intel 430 TX PCISET: 82439 TX System Controller (MTXC)”, Feb. 1997.
Nakase et al., “Source Synchronization and Timing Vernier Techniques for 1.2-GB/s SLDRAM Interface”,IEEE J. Solid-State Circuits, vol. 34, No. 4, Apr. 1999.
Paris et al., “WP 24.3: An 800 MB/s 72 Mb SLDRAM with Digitally-Calibrated DLL”, ISSCC Slide Supplement, IEEE, 1999.
SLDRAM Inc., “400/Mb/s/pin”, Jul. 9, 1998.
Barth Richard M.
Donnelly Kevin S.
Hampel Craig E.
Horowitz Mark A.
Moncayo Alfredo
Auve Glenn A.
Morgan & Lewis & Bockius, LLP
Rambus Inc.
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