Electrical computers and digital data processing systems: input/ – Intrasystem connection – System configuring
Reexamination Certificate
2001-07-19
2003-02-04
Auve, Glenn A. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
System configuring
C326S030000, C710S302000
Reexamination Certificate
active
06516365
ABSTRACT:
The present invention relates generally to a bus system, and particularly to a bus system capable of adjusting signal characteristics in response to topography dependent parameters.
BACKGROUND OF THE INVENTION
A bus system is a chip-to-chip electronic communications system in which one or more slave devices are connected to, and communicate with, a master device through shared bus signal lines.
FIG. 1
illustrates in block diagram form a bus system. The bus system includes a Master control device (M) that communicates with one or more Slave devices (D) via a bi-directional data bus. Typically, the bi-directional data bus comprises a plurality of bus signal lines, but for simplicity,
FIG. 1
illustrates only one bus signal line. The terms bus signal line and channel are used synonymously herein. Thus, it will be understood that the data bus includes many channels, one for each bit of data. Each bus signal line terminates on one side at an I/O pin of the master device and terminates on its other side at one end of a resistive terminator (T). The resistance of the terminator is closely matched to the loaded impedance, Z
L
, of the bus signal line to minimize reflections and absorb signals sent down the bus signal line toward the terminator. The opposite end of the terminator is connected to a voltage supply that provides an AC ground and sets the DC termination voltage of the bus signal line. The positions along the bus signal line tapped by the Master terminator, and Slaves are labeled p
M
, p
T
, and p
1
- - - p
N
, respectively.
Bus systems are typically designed to work with several configurations to allow system flexibility. For example, the bus may have several connector slots for inserting individual Slaves or Modules of Slaves, and each Module may have different numbers of devices. This allows the user to change the number of chips that operate in the bus system, allowing small, medium, and large systems to be configured without complex engineering changes, such as changes to the printed circuit board layout.
FIG. 2
illustrates a Bus System that provides this flexibility by providing three connectors for three Slave Modules. This figure does not necessarily illustrate the physical layout of an actual system, but shows the electrical connections of the Bus System. The first Module is shown with eight Slaves, the second with four Slaves, and the third Modules with no Slaves. The third Module serves only to electrically connect the terminator to the bus signal line. For simplicity, this configuration can be referred to as an
8
-
4
-
0
configuration, and many other configurations are possible by inserting different Modules into the three connector slots (e.g.
8
-
8
-
8
,
4
-
0
-
0
, etc.). As in
FIG. 1
,
FIG. 2
designates the points at which each device taps the bus signal line (e.g. Slave B
2
taps the bus signal line at point p
B2
). The Bus System of
FIG. 2
is very flexible; however, this flexibility results in configuration-dependent and position-dependent channel characteristics that lead to signaling complexities and reduce the reliability of data transmission through the system.
FIG. 3
diagrams structure and electrical properties of a bus signal line in a populated Module of the Bus System of FIG.
2
. The portion of the bus signal line that connects to the Slaves forms a repetitive structure of signal line segments and Slaves that can be modeled as a transmission line of length d, with electrical characteristics as shown. In
FIG. 3
L
o
is the inductance per unit length, C
o
is the capacitance per unit length, G
p
is the dielectric conductance per unit length, and R
s
is the conductor resistance per unit length. The lossy, complex characteristic impedance of such transmission line is given by:
Z
OL
=
R
S
+
jω
L
O
G
P
+
jω
C
l
However, assuming R
s
and G
p
are small, the characteristic impedance of the bus signal line segment is closely approximated by the simpler equation Zo={square root over (Lo/Co)}.
FIG. 3
also shows the dominant electrical properties of the Slaves I/O pins where L
I
is the effective input inductance, C
I
is the effective input capacitance, and R
1
is the effective input resistance. This input resistance incorporates all input losses including metallic, ohmic, and on-chip substrate losses; is frequency dependent; and tends to increase with frequency. However, assuming that the input capacitance dominates the input electrical characteristics of the Slave (i.e. Xc=1/(2&pgr;fC
1
)>>X
L
=2&pgr;fL
1
and Xc=1/(2&pgr;fC
1
)>>R
1
) at the system operating frequency, the effective loaded impedance of the bus signal lines is closely approximated by:
Z
L
=
L
o
·
d
(
C
o
·
d
)
+
C
l
This equation implies that the lumped capacitance of the Slaves' I/O pins is distributed into the effective impedance of the transmission lines. However, the repetitive arrangement of Slaves at intervals of length d along the bus signal line causes the bus signal line to possess a multi-pole low-pass filter characteristic. This lowpass characteristic essentially limits the maximum data transfer rate of the bus system. The cut-off frequency of the channel increases as the number of devices on the channel decreases; as the device spacing, d, decreases; and as the input capacitance, C
I
, decreases.
FIGS. 4
,
5
and
6
, illustrate these effects. Additionally, dissipative sources of loss such as the dielectric of the bus' printed circuit board substrate, the skin effect resistance of the bus' metal traces, and the slave devices' input resistances, R
I
, also contribute to the low-pass characteristic of the bus signal line, further reducing the usable bandwidth.
FIG. 7
illustrates this. For any number of Slaves, it is clearly desirable to have minimum device pitch, d; minimum input capacitance, C
I
; and minimum loss (e.g. R
I
) for maximum frequency operation of the system.
For these reasons, the device pitch, d, is generally kept at a fixed, minimum practical length which is determined by space limitations and printed circuit board technology. Likewise input capacitance is kept to a fairly tight, minimum range determined by silicon ESD requirements and processing limitations. Losses are also typically controlled within a specified range. Therefore, although there is some variation in these three factors, the major determinant of the channel's response and bandwidth is the configuration and number of devices. This is illustrated in FIG.
8
.
FIG. 8
illustrates the channel response from the Master to the last Slave device on the channel (i.e. the forward transmission to device D
N
) for three system configurations,
16
-
8
-
8
,
84
-
0
, and
4
-
0
-
0
. The solid line for each configuration plots the typical response while the shading around each line indicates the range of likely channel responses for that configuration considering manufacturing variations in device pitch, input capacitance, and loss (both R
1
and channel losses).
FIG. 8
suggests that the channel characteristics are largely determined by the system configuration, such that transmission of data through Bus System (to the last device) depends strongly on the configuration used (i.e. number and type of modules used). Thus, it may be possible to improve the performance of the Bus System by adjusting transmitter or receiver parameters in response to the particular system configuration that is being used in order to compensate for the configuration-dependent transmission characteristics.
FIG. 9
illustrates the channel response between the Master and the first, middle, and last Slaves in an N-device Bus System. The solid lines in
FIG. 9
plot the typical response for the first, middle, and Nth device while the shading around each line indicates the range of likely channel responses for that device position considering manufacturing variations in device pitch, input capacitance, and loss.
FIG. 9
suggests that for a given channel configuration, the chann
Barth Richard M.
Donnelly Kevin S.
Hampel Craig E.
Horowitz Mark A.
Moncayo Alfredo
Auve Glenn A.
Pennie & Edmonds LLP
Rambus Inc.
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