Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
1999-09-23
2002-04-16
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S212000, C365S063000, C365S052000
Reexamination Certificate
active
06373768
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to thermal regulation of memory devices in a memory system. More particularly, the present invention relates to an apparatus and method used to control operation of a memory system to regulate the operating temperature of memory devices in the memory system.
BACKGROUND OF THE INVENTION
Improvements in microprocessor designs have led to microprocessors with a high operating frequency. Current microprocessor designs have operating frequencies of 400 megahertz (“MHz”) and higher. The increase in operating frequency, however, has not led to fully acceptable performance gains. One of the main factors adversely affecting performance gains is created when the microprocessor idles during delays in external memory access. The delays in external memory access are caused by the conventional design characteristics of static random access memory (“SRAM”) cells, read only memory (“ROM”) cells, and dynamic random access memory (“DRAM”) cells.
To counteract the performance losses associated with external memory access, Rambus Inc., of Mountain View, Calif., developed a high speed memory system.
FIG. 1
illustrates the Rambus high speed memory system. In particular, system
100
shows a master device, memory controller (“MC”)
10
, coupled to memory devices DRAM
20
, SRAM
30
, and ROM
40
. Each device is coupled in parallel to signal lines DATA BUS, ADDR BUS, CLOCK, V
REF
, GND, and VDD. DATA BUS and ADDR BUS show the data and address lines used by MC
10
to access data from the memory devices. CLOCK, V
REF
, GND, and VDD are the clock, voltage reference, ground, and power signals shared between the multiple devices. Data is transferred by memory device bus drivers (not shown) driving signals onto the bus. The signals are transmitted over the bus to a destination device, such as MC
10
or a central processing unit (“CPU”) (not shown). Accordingly, MC
10
coordinates the data transfer between the memory devices of system
100
and a destination device.
To increase the memory access speed, system
100
supports large data block transfers between the input/output (“I/O”) pins of the destination device and the memory devices of system
100
. System
100
may also include design requirements that constrain the length of the transmission bus, the pitch between the bus lines, and the capacitive loading on the bus lines. Using these design requirements system
100
operates at a higher frequency than conventional memory systems. Accordingly, by increasing operating frequency the performance of system
100
increases, thus reducing the idle time of the destination device coupled to system
100
.
Although a high operating frequency increases data throughput, operating system
100
at a high frequency typically results in higher power dissipation and correspondingly higher system temperatures. This result is not unexpected when the basic concept of thermal capacities is considered. The heat curve shown in
FIG. 2
illustrates this concept.
Beginning at some ambient temperature (T, ambient), the temperature of an electrical device will rise over time to a maximum, steady state temperature (T, steady state) as constant power is applied. The rate at which the temperature rises is determined by the thermal capacity of the device. The steady state temperature is defined by many factors including the geometry, size, composition, and surrounding environment (such as air flow) of the device.
In the particular case of memory devices in a memory system, power is not constant. Rather, the memory device is switched ON and OFF with individual data requests. Thus, the heating curve for a memory device will fluctuate considerably depending on it use in addition to its thermal capacity.
Excessive heating of a memory device may cause problems well below the steady state temperature. In fact, memory devices are designed to operate at temperatures below a given junction temperature (“Tj
,max
”)
Additionally, provided the memory device includes a dynamic cell design, its specification will also include a defined periodic refresh rate. The refresh rate ensures that the storage cells of the dynamic device are periodically recharged. Increasing the operating frequency of a memory system, however, results in the memory devices of the memory system generating high power levels. The high power levels translate into an increase in the operating temperature of the memory devices. If the operating temperature of a memory device surpasses Tj
,max
the memory device may fail, thus resulting in the failure of the memory system.
To ensure lower operating temperatures, prior art memory systems implement conventional thermal management techniques. In particular, to reduce the operating temperature of a memory device, prior art memory systems typically use specific packaging designs and specify the location of memory devices in memory systems. Conventional thermal management techniques, however, create numerous disadvantages.
In fact, many of the conventional thermal management techniques are not readily applicable to evolving high frequency memory systems. Conventional thermal management using packaging designs for the memory devices is a good example. In particular, conventional packaging designs are not always effective for dissipating heat generated by memory devices operating at frequencies in excess of 100 Mhz. Accordingly, the application of traditional packaging designs to reduce thermal dissipation prove ineffective in the thermal regulation of system
100
.
Conventional thermal management techniques based on the design layout of memory systems is another good example. In particular, such conventional thermal management techniques require large spacings between components to reduce heat transfer. In system
100
, however, the devices are located in relatively close proximity to one another in order to increase data throughput. Accordingly, the application of conventional placement techniques to reduce thermal dissipation prove ineffective in the thermal regulation of system
100
.
SUMMARY OF THE INVENTION
In view of the foregoing, a brief summary of some exemplary embodiments will now be presented. Some simplifications and omissions may be made in this summary, which is intended to highlight and introduce some aspects of the present invention, but not to limit its scope in any way. Detailed descriptions of the preferred embodiments adequate to allow those of ordinary skill in the art to make and use the inventive concepts are provided hereafter.
The present invention provides a system and method for thermal regulation of a memory system. Memory systems operating at high frequencies are particularly well adapted to the present invention. That is, despite the fact that high frequency operation results in greater power dissipation and increased heat, the present invention yet allows the memory devices in the system to operate below a specified junction temperature, or in the alternative to reliably operate at temperatures above the specified junction temperature with appropriate modification of the system's performance parameters.
In one embodiment of the present invention, the operating temperature of the memory device(s) is estimated. In another embodiment, the actual operating temperature of the memory devices(s) is measured. In either embodiment, operating temperature may be derived on a memory device by memory device basis, or on a memory module basis.
For example, one aspect the present invention provides a memory system comprising a memory controller coupled to a bus, and at least one memory device coupled to the bus. Typically there are a plurality N of memory devices coupled to the bus. The memory controller comprises a tracking circuit operable to track a number of memory device operations involving M of the N memory devices during a period of time, where M is less than or equal to N. The memory controller also comprises a control circuit operable to manipulate operation of the memory system in response to a comparison of the number of memory operations and a
Barth Richard M.
Hampel Craig E.
Satagopan Ramprasad
Tsern Ely K.
Woo Steven C.
Auduong Gene N.
Nelms David
Rambus Inc
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