Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2001-08-13
2004-02-10
Cuneo, Kamand (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S763010, C324S1540PB, C714S733000, C714S734000
Reexamination Certificate
active
06690189
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an apparatus for testing a semiconductor integrated circuit, and more particularly to an apparatus and method for testing a semiconductor integrated circuit including an A/D (analog-to-digital) converter circuit for converting an analog signal into a digital signal and a D/A (digital-to-analog) converter circuit for converting a digital signal into an analog signal.
2. Background Art
Recently, in relation to a system LSI embodied in a one-chip semiconductor integrated circuit (a one-chip LSI) consisting of a plurality of functionally-systematized circuit modules or embodied in a hybrid integrated circuit (a chip set LSI), combination of high-performance and precision digital and analog circuits (i.e., a system LSI handling a mixed signal) has been rapidly pursued. Even in relation to a test apparatus for use with a semiconductor integrated circuit, development of a test apparatus capable of handling a mixed signal is also pursued. Tester manufacturers have provided testers coping with a semiconductor integrated circuit using a mixed signal.
A tester compatible with a semiconductor integrated circuit using a mixed signal has a tendency to become expensive in the course of ensuring compliance with high performance specifications. For this reason, moves are afoot to recycle an existing low-speed, low-precision tester which has been used for, e.g., a logic LSI, to thereby avoid a hike in the price of a tester.
A big problem with such a test apparatus lies in a characteristic test for a D/A converter circuit for converting a digital signal into an analog signal (digital-to-analog converter, hereinafter called a “DAC”) as well as in a characteristic test for an A/D converter circuit for converting an analog signal into a digital signal (hereinafter called an “ADC”). In association with an increase in the precision of the characteristic test, embodiment of a low-cost test apparatus compatible with a semiconductor integrated circuit including the DAC and ADC has posed a challenge.
In a testing environment of a general tester, a plurality of DUT (device under test) circuit boards (simply called “DUT boards”) and connection jigs for connecting a tester with a DUT, such as cables, are provided at a plurality of points along a measurement path extending from measurement equipment provided in the tester to a semiconductor integrated circuit under test (hereinafter called a “DUT”). Further, the measurement path is long and accounts for occurrence of noise and a drop in measurement accuracy. Further, simultaneous testing of a plurality of DUTs is also impossible. A limitation is imposed on the speed of a low-speed tester, and hence the low-speed tester cannot conduct a test at a real operating speed, thereby posing a fear of an increase in a time required for conducting mass-production testing of a system LSI.
Japanese Patent Application Laid-Open No. 316024/1989 describes a tester. The tester is equipped with a memory device for storing conversion data at an address designated by input data which have been entered into a DAC of a test circuit. An analog signal which has been subjected to digital-to-analog conversion is inputted to an ADC, and an output from the ADC is sequentially stored in the memory device. After conversion of all the input data sets has been completed, the conversion data stored in the memory device are sequentially delivered to a tester. The tester sequentially compares the input data with the conversion data, thus producing a test conclusion.
However, the tester must supply data to be inputted to the DAC, an address to be used for storing conversion data into a memory device, and a control signal. Moreover, data stored in the memory device must be supplied to the tester. Further, there is the probability that noise arising in a long measurement path extending from the tester to a DUT may deteriorate precision of measurement. Further, the majority of pin electronics provided on the tester are occupied for testing a single DUT, thereby posing a difficulty in simultaneous measurement of a plurality of DUTs.
Further, communication for transmitting conversion data to the tester is time consuming, and test conclusions are produced after completion of all tests. Hence, shortening of a test time is also difficult.
SUMMARY OF THE INVENTION
The present invention has been conceived to solve such a problem and is aimed at providing an apparatus and method of testing a semiconductor integrated circuit, which apparatus and method facilitate operation of a BOST device and improve the convenience thereof.
According to one aspect of the present invention, an apparatus for testing a semiconductor integrated circuit comprises a test circuit board configured to transmit signals to and receive signals from a semiconductor integrated circuit to be tested that comprises an A/D converter circuit to convert analog signals to digital signals and a D/A converter circuit to convert digital signals to analog signals, a test ancillary device which is disposed in the vicinity of the test circuit board and is connected to the test circuit board, and an external controller which assigns a numeric code to a test on the semiconductor integrated circuit to be performed by the test ancillary device and which transmits the numeric code to the test ancillary device. The test ancillary device comprises memory having stored therein a test requirement table in which hardware requirements required for conducting a test are set on a per-numeric-code, an analysis section for reading test requirements corresponding to the numeric code from the test requirement table; a data circuit which supplies a digital test signal to the D/A converter circuit of the semiconductor integrated circuit to be tested on the basis of the test requirements, a testing D/A converter circuit which converts the digital test signal from the data circuit into an analog test signal and supplies the analog test signal to the A/D converter circuit of the semiconductor integrated circuit to be tested, a testing A/D converter circuit which converts an analog test output from the D/A converter circuit of the semiconductor integrated circuit to be tested into a digital test output, and measured data memory for storing a digital test output from the A/D converter circuit of the semiconductor integrated circuit to be tested and the digital test output from the testing A/D converter circuit. A result of analysis of the each digital test outputs stored in the measured data memory, the analysis being performed by the analysis section, is sent to the external controller.
By means of the test apparatus and the test method according to the present invention, numeric codes are assigned to tests to be performed by a DUT. The test apparatus is equipped with memory, and a test requirement table having stored therein specification evaluation values stored therein. A test requirement table in which hardware requirements required for conducting a test are set for each numeric code is stored in the memory. Test requirements corresponding to the numeric code are read from the test requirement table, and a test is performed. A result of test is compared with specification evaluation values, whereby the test result is evaluated. Thus, evaluation of a test result as well as conduction of a test can be performed in the BOST device. Thus, there is no necessity of acquiring measured data into a tester. Hence, the ease of operation and convenience of the BOST device are improved, shortening of a test time becomes feasible.
Other and further objects, features and advantages of the invention will appear more fully from the following description.
REFERENCES:
patent: 6028431 (2000-02-01), Hashida
patent: 6408412 (2002-06-01), Rajsuman
patent: 6449741 (2002-09-01), Organ et al.
patent: 8-233912 (1996-09-01), None
patent: 9-189750 (1997-07-01), None
Funakura Teruhiko
Mori Hisaya
Yamada Shinji
Chan Emily Y
Cuneo Kamand
McDermott & Will & Emery
Renesas Technology Corp.
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