Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1999-12-03
2003-03-04
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S819000, C365S201000, C365S230030
Reexamination Certificate
active
06530045
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor wafer testing and more particularly to an apparatus and method for reducing the pin count necessary to test Rambus dynamic random access memory (RDRAM).
2. Description of the Related Art
Rambus DRAM (RDRAM) is a general-purpose, high-performance, packet-oriented dynamic random-access memory device suitable for use in a broad range of applications, including computer memory, graphics, video, and other applications.
FIG. 1
schematically illustrates a RDRAM device
10
interconnected with a central processing unit
11
as part of a typical computer system. The RDRAM
10
receives clock signals
12
, control logic
14
and address information
16
from the CPU
11
via a controller
20
. Data
17
is written to and read from the RDRAM
10
.
FIG. 2
is a block diagram illustrating one RDRAM configuration in the normal mode. The RDRAM comprises two major blocks: a “core” block
18
comprising banks
22
, sense amps
24
and I/O gating
26
similar to those found in other types of DRAM, and a control logic: block
19
which permits an external controller
10
to access the core
18
. The RDRAM core
18
is internally configured as
32
banks
22
. Each bank
22
has 32,768 144-bit storage locations.
FIG. 3
is a diagram indicating that each of the banks
22
is organized as 512 rows
28
by 64 columns
30
by 144 bits
32
. The 144 bits
32
in each column
30
are serially multiplexed onto the RDRAM's I/O pins as eight 18-bit words
34
. The most significant bits
17
-
9
are communicated on I/O pins DQA <
8
:
0
>, and the least significant bits
8
-
0
are communicated on the I/O pins DQB <
8
:
0
>. The nine. bits on each set of pins are output or input on successive clock edges so that the bits in the eight words are transferred on eight clock edges. The control logic
19
in
FIG. 2
receives the CMD, SCK, SIO
0
, and SIO
1
strobes that supply the RDRAM configuration information to the controller
10
, and that select the operating modes of the chip
10
. The CFM, CFMN, CTM and CTNN pins generate the internal clocks used to transmit read data, receive write data, and receive the row and column pins used to manage the transfer of data between the banks
22
and the sense amps
24
of the RDRAM
10
.
Eight RQ pins carry control and address information. The RQ pins are divided into two groups. Three ROW pins are de-multiplexed into row packets that manage the transfer of data between the banks
22
and the sense amps
24
. Five COL pins are de-multiplexed into column packets and manage the transfer of data between the data pins and the sense amps
24
of the RDRAM
10
. More detailed information on the operation of RDRAM can be found in Reference A, Direct RDRAM Preliminary Information, Document DL0059 Version 0.9 by Rambus Inc. which is incorporated herein by reference.
Semiconductor chips, such as RDRAM chips
10
, contain circuit elements formed in the semiconductor layers which make up the integrated circuits.
FIGS. 4A and 4B
illustrate a chip
10
with exposed bonding pads
46
made of metal, such as aluminum or the like that are formed as terminals of integrated circuits. In normal operation, the control signals
14
, the address signals
16
, and the data
17
are exchanged with the CPU
11
through connections at these bonding pads
46
.
In the manufacturing process, a large number of semiconductor chips
10
, each having a predetermined circuit pattern, are formed on a semiconductor wafer
48
such as that shown in FIG.
5
.
FIG. 5
illustrates the semiconductor wafer
48
prior to being diced into individual semiconductor chips. Although
FIG. 5
only shows a relatively small number of chips on the wafer, one skilled in the art will appreciate that many chips can be cut from a single wafer. The semiconductor chips
10
are subjected to electrical characteristic tests while they are on the wafer
48
through the use of a testing apparatus, e.g., a wafer probe
50
having a plurality of pins
52
. Note that only the head of the wafer probe
50
is shown in FIG.
5
. Wafer probe testing is commonly used to quality sort individual chips
10
before they are diced from the wafer
48
. The primary goal of wafer probe testing is to identify and mark for easy discrimination defective chips early in the manufacturing process. Wafer testing significantly improves manufacturing efficiency and product quality by detecting defects at the earliest possible stages in the manufacturing and assembly process. In some circumstances, wafer probe testing, provides information to enable certain defects to be corrected.
FIG. 6
shows a plurality of the conductive pins
52
of the wafer probe
50
of FIG.
5
. The pins have respective tip ends
54
positionally adjusted to align with the bonding pads
46
of the chip
10
to be tested. A wafer probe
50
has a limited number of pins
52
(e.g., 100 pins) available to supply the test signals to the chips
10
in the wafer
48
. The chips
10
could be tested in their normal mode, but this would require in excess of 40 pins
52
on the wafer probe
50
to test each chip
10
. Others have recognized the benefits of creating a special test mode that enables a chip to be tested with fewer pins. Therefore, one skilled in the art will recognize that it is not required to have a pin
52
for every bonding pad
46
on the chip
10
. However, prior testing methodology references such as Direct RDRAM Test Mode Specification Revision 0.5, Rambus Confidential Information, for RDRAM chips requires at least 34 pins
52
on the wafer probe
50
to test each Rambus DRAM chip
10
, thus constraining the 100 pin wafer probe to test, at most, two chips at one time. As a result, the production time and chip costs are negatively impacted by this limitation.
As set forth above, the prior art method of wafer testing RDRAM chips requires 34 pins
52
to test each chip
10
, of which 18 pins are address and data pins. Following this method, the first operation in selecting the address on the RDRAM core entails precharging the bank
22
. Precharging is necessary because adjacent banks
22
share the same sense amps
4
and cannot, therefore be simultaneously activated. Precharging a particular bank
22
deactivates the particular bank and prepares that bank
22
and the sense amps
24
for subsequent activation. For example, when the row
28
in the particular bank
22
is activated, the two adjacent sense amps
24
are connected to or associated with that bank, and therefore are not available for use by the two adjacent banks. Precharging, the bank
22
also automatically causes the two adjacent banks to be precharged, thereby ensuring that adjacent banks are not activated at the same time.
Selecting one of the 32 banks
22
to precharge requires five address bits to specify the bank address. These address bits are provided in a first control signal. The next operation in selecting an address is activating a row
28
in a selected bank using a second control signal. This operation requires nine address bits to select one of the 512 rows
28
, and five address bits to select one of the
32
banks
22
, for a total of 14 address bits. The next operation reads a column
30
in an open bank using a third control signal.
This operation requires five bank bits. This operation also requires six column bits to select one of the 64 columns
30
.
Reducing the number of address bits required to specify the address location to be tested reduces the number of pin connections
52
required on the wafer probe
50
to test each individual chip
10
. Reducing the required number of pin connections
52
therefore allows more chips
10
to be tested at the same time, thus permitting an important reduction in production time and chip costs. As chip sizes continue to decrease, there i.; a corresponding increase in the number of chips on each semiconductor wafer to be tested. Therefore, the ability to test an increased number of devices at the same time grows in impor
Ayres Scott L.
Cooper Christopher B.
Giam Siang Tian
McBride Jerry D.
De'cady Albert
Dooley Matthew C.
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