Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
1996-11-12
2003-09-23
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S226000, 37
Reexamination Certificate
active
06625073
ABSTRACT:
TECHNICAL FIELD
The present invention relates to apparatus and methods for testing semiconductor electrical devices, particularly memory devices.
BACKGROUND OF THE INVENTION
Various types of defects and failures can occur during the manufacture of semiconductor devices. A “failure” occurs when a semiconductor device fails to meet its specifications. A “defect” occurs when a semiconductor device has an improper circuit structure that currently presents a failure of the device, or has the potential to fail during the expected lifetime of the device. For example, due to a manufacturing error, an insulator or dielectric between a pair of memory cells can be thinned or include polysilicon particles which could currently provide a short therebetween, or could break down over a period of time (“a cell-to-cell defect”). After this period of time, typically during prolonged use of tie device, the polysilicon particle provides a conductive path between the cells so that a “high” voltage written to one cell forces a “low” voltage on an adjacent cell to rise to a high value, resulting in a failure.
Therefore, a polysilicon particle that presently shorts two memory cells together is a defect resulting in a failure of the semiconductor device. A polysilicon particle that has not yet formed a short between the two memory cells, however, is a defect that has not yet evidenced itself as a failure. As a result, the semiconductor device can be operated for a brief time under standard operating conditions and voltages before the defect manifests itself as a failure.
Testing is performed on semiconductor devices to locate defects and failures in such devices. As circuit density on semiconductor devices increases, the number of defects and failures can increase. Semiconductor manufacturers, therefore, have an increasing need to detect for defects and failures in semiconductor devices as circuit density on these devices increases.
Thus, for quality control and to improve yields of acceptably operable semiconductor devices, semiconductor devices are tested, often before a die containing the semiconductor device is packaged into a chip. A series of probes on a test station electrically contact pads on each die in a wafer to thereby access portions of the individual semiconductor devices on the die. For example, in a semiconductor memory device, the probes contact address and data input/output pads to access selected memory cells in the memory device. Typical dynamic random access memory devices (“DRAM”) include one or more arrays of memory cells that are each arranged in rows and columns. Each array of memory cells includes word or row lines that select memory cells along a selected row, and bit, digit or column lines (or pairs of lines) that select individual memory cells along a row to read data from, or write data to, the cells in the selected row.
During testing, predetermined data or voltage values are typically written to selected row addresses, or row and column addresses, that correspond to certain memory cells, and then the voltage values are read from those memory cells to determine if the read data matches the data written to those addresses. If the read data does not match the written data, then the memory cells at the selected addresses likely contain defects and the semiconductor devices fail the test.
A person testing the several dies on the wafer can then examine a particular die itself, by means of a microscope, to determine if failures occurred from masking defects, during the deposition of certain layers, and so forth. During the initial development of a semiconductor device, and while the device is in die form, changes to masks can be made to compensate for most detected failures. However, once a semiconductor device is in production and packaged as a chip, redundant circuitry on the semiconductor device can be employed to compensate for only certain detected failures. Redundant circuitry on the semiconductor device cannot compensate for many detected failures, and therefore, such failed devices must generally be discarded.
Semiconductor manufacturers, to increase output of acceptable semiconductor devices, strive to perform rapid testing of the semiconductor devices to expose defects in the devices before shipping them to a vendor or user. A semiconductor device can be most thoroughly tested when the device is still in die form on the semiconductor wafer. Semiconductor wafers, however, are often difficult to manipulate, and typically require a test bed or other apparatus to releasably secure the wafer while the probes are adjusted to contact the pads on each die on the wafer. As a result, testing of semiconductor devices in die form is time consuming. Therefore, semiconductor manufacturers desire to test a given semiconductor device after it has been packaged as a semiconductor chip, because the chip can be automatically inserted into a test socket for testing using pick and place machinery. Automated testing circuitry can then apply predetermined voltages and signals to the chip, write test patterns thereto, and analyze the results therefrom to detect for failures in the chip.
Often, the number of pads on a die is greater than the number of pins on the packaged semiconductor chip. Therefore, as noted above, certain tests performed while the semiconductor device is in die form cannot be performed on the device after it has been packaged. As a result, package chips necessarily undergo less rigorous testing than unpackaged dies. Packaged chips therefore can include manufacturing defects that are not yet failures and thus are undetectable by the limited number of tests capable of being performed on the packaged chips.
For example, to test for the above-identified cell-to-cell defect, a test circuit writes a pattern of higher than average voltage values (as logical “1” values) to memory cells coupled to or “along” several row lines, while writing low voltage values (as logical “0” values) to memory cells along the adjacent row lines. The test circuit then determines whether the memory cells along the adjacent row lines maintain a logical “0” value. If not, then the logical “1” value written to a first memory cell has shorted to an adjacent memory cell, causing the low voltage or logical “0” value to rise to become a high voltage or logical “1” value.
The time required for the high voltage value in the first memory cell to raise the voltage in the adjacent memory cell will vary depending upon the severity of the defect between the cells. As a result, a high voltage value over a continuous period of time must be applied to the memory cells along the first row lines to force the failure to the memory cells along the adjacent row lines. External test circuitry typically must apply such a continuous, high voltage value to the semiconductor memory device while the device is still in its die form.
Some semiconductor memory devices include an on-chip voltage pump that provides a boosted voltage, greater than the supply voltage Vcc, that can provide the continuous, high voltage value to memory cells along several row lines. However, typical 16 megabit DRAM circuits contain 4096 row lines. As a result, to test only memory cells along half of the row lines over the period required to force a cell-to-cell defect, when the voltage pump can activate only several row lines at a time, requires a prolonged test cycle for each packaged chip. Consequently, cell-to-cell defects cannot be efficiently tested in packaged chips. As a result, cell-to-cell defects can typically only be tested efficiently when the semiconductor memory device is in die form. Probes access the voltage pump circuit and apply supplemental power to the device being tested to thereby simultaneously provide the high voltage value to multiple row lines over the continuous test period. Such a cell-to-cell stress test, however, suffers from the above-described difficulties in testing semiconductor memory circuits when in die form. Therefore, any time saved by conducting the cell-to-cell stress test while the semiconductor device is in d
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Nguyen Viet Q.
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