Apparatus and method for testing a memory

Details Apparatus and method for testing a memory Apparatus and method for testing a memory

1998-04-14

1999-01-19

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Testing

36518901, Q11C 1300

Patent

active

058620885

ABSTRACT:
In a memory testing apparatus wherein a plurality of function tests are continuously carried out for a semiconductor memory and a decision as to whether or not a failure relieving analysis of the memory should be performed is rendered upon completion of each function test, a failure cell counter 15 is provided at the rear stage of a failure analysis memory 13. When a failure memory cell is detected in a memory under test MUT in each function test, the number of failure cells of the memory under test is counted by the failure cell counter. A main controller controls operations of the memory testing apparatus ST such that a failure relieving analysis of the memory under test is performed only when the number of failure memory cells detected in the function test performed this time is greater than the number of failure memory cells detected in the preceding function test.

REFERENCES:
patent: 5691945 (1997-11-01), Liou et al.

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