Semiconductor device manufacturing: process – With measuring or testing – Packaging or treatment of packaged semiconductor
Patent
1998-05-08
2000-09-12
Whitehead, Jr., Carl
Semiconductor device manufacturing: process
With measuring or testing
Packaging or treatment of packaged semiconductor
438108, 73827, H01L 2144
Patent
active
061176958
ABSTRACT:
An apparatus and method are presented for testing an adhesive layer formed between an integrated circuit and a plate, wherein the plate may be semiconductor device package substrate or a heat spreader. The apparatus includes a pull stud and a pull arm. The pull stud has an upper portion and a lower portion, wherein the lower portion is attached to a surface of the integrated circuit opposite the plate. The upper portion of the pull stud may be, for example, a tapered cylinder having a large end and a small end. The small end meets the lower portion of the pull stud. The pull arm has two opposed ends and at least one bracket for receiving a force. One of the pull arm ends has a "V"-shaped opening surrounded by a lip which receives the upper portion of the pull stud. During use, the lip contacts and retains the upper portion of the pull stud. The opening has an upper wall, and an upper surface of the pull stud contacts the upper wall when the upper portion of the pull stud is inserted into the opening. The lip is vertically displaced from the upper wall such that the lip contacts the upper portion of the pull stud a spaced distance from where the upper surface of the pull stud contacts the upper wall of the opening. In this way, the pull stud and the pull arm are substantially mechanically locked together during use of the apparatus.
REFERENCES:
patent: 3634930 (1972-01-01), Cranston
patent: 5164037 (1992-11-01), Iwami et al.
patent: 5313841 (1994-05-01), Layher
patent: 5337614 (1994-08-01), Jiang et al.
Murphy Adrian S.
Thavarajah Manickam
Variot Patrick J.
Jr. Carl Whitehead
Kivlin B. Noel
LSI Logic Corporation
Vockrodt Jeff
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