Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-08-21
2007-08-21
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C714S738000
Reexamination Certificate
active
09985768
ABSTRACT:
Based on the concept of minimization, a method of static compaction has been developed for a digital circuit. The compaction method is a combination of two main procedures: one for the selection of essential test stimuli and the other for the elimination of redundant test stimuli, and effective in minimizing any set of test stimuli without modifying any of the test stimuli.
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Siek Vuthe
Staas & Halsey , LLP
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