Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-04-09
2001-03-27
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06209119
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the technology for synthesizing a layout module for a data path circuit used in an LSI including a CMOS.
In recent years, a degree of integration and a clock frequency of an LSI have been increased continuously. According to current estimates the number of transistors per unit area of 1 cm
2
in an LSI will reach 18 millions in 2003, while the clock frequency used therein will be as high as 500 MHz (ASP-DAC '98, Tutorial 3, “Analysis/Optimization of Performance and Noise in Deep Submicron Designs,” Tuesday, Feb. 10, 1998).
Under such circumstances, LSI manufacturing has entered a deep submicron era and LSI design has become increasingly complicated. For example, since the wiring spacing has been minimized to approximately 0.1 &mgr;m, delay and power consumption are more dependent on wiring load than on gate capacitance. Thus, it has become extremely difficult to evaluate the delay, power consumption, and clock skew of an LSI in the upper process of design (functional level and RTL level). The minimized wiring spacing also requires a wiring model, used for estimating a wiring delay, to reflect the influence of the coupling capacitance of wires. However, it is substantially impossible to estimate the coupling capacitance of wires in the upper process of design.
Consequently, the capability to correct the result of the upper process of design in the lower process of design (logic level and transistor level) becomes extremely important. By establishing a close linkage between the evaluating capability in the upper process of design and the correcting capability in the lower process of design, iteration in the LSI design can be lessened, which reduces design cost and implements higher-quality LSI design.
To establish a close linkage between the upper and lower processes of design, it is necessary to provide, from the lower side of design, accurate data about the performance and area of a module required by the upper side of design in a shorter period of time. In short, a module synthesizing apparatus used in the lower process of design should have a capability of instantaneously estimating the results of syntheses with respect to a plurality of conditions in order that a tool for synthesis used in the upper process of design can explore a design space for optimizing module allocation and binding. However, the conventional module synthesizing apparatus does not have such a capability and merely synthesizes a layout module with respect to a single condition. If the performance and area of a module are to be estimated with respect to a plurality of conditions, therefore, the conventional module synthesizing apparatus has no other alternative than to actually synthesize the module with respect to each of the conditions, which wastes a great deal of processing time.
In addition, since a cell used in the conventional module synthesizing apparatus has substantially no geometrical flexibility, a dead area is likely to arise when a cell having an optimum driving ability is selected. As a result, the geometry of a layout module cannot be optimized with accuracy.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide an apparatus and method for synthesizing a module for a data path circuit, which can optimize the geometry of a layout module with high accuracy and can easily establish a close linkage to the upper process of design.
Specifically, the present invention provides a module synthesizing apparatus for synthesizing a layout module for a data path circuit, including: a logic-level processing unit for specifying cells in the data path circuit based on logic circuit data representing the data path circuit on a logic level; a cell-property estimating unit for obtaining a geometrical function parameterized by delay for a cell provided with a circuit configuration on a transistor level; and a synthesis processing unit for setting circuit configurations on the transistor level for the respective cells specified by said logic-level processing unit, supplying the set circuit configurations on the transistor level to the cell-property estimating unit, and then synthesizing a layout module based on geometrical functions of the respective cells, which have been parameterized by delays and have been obtained by the cell-property estimating unit.
According to the present invention, a geometrical function parameterized by delay can be generated for each of the cells in the data path circuit, which have been specified by the logic-level processing unit, based on the transistor-level circuit configuration supplied from the synthesis processing unit. As a result, a cell in the data path circuit has higher geometrical flexibility as compared with a conventional apparatus. Since the synthesis processing unit synthesizes a layout module by using the cell geometrical function parameterized by delay, a dead area between cells can be reduced and the geometry of the layout module can be optimized with higher accuracy as compared with a conventional apparatus.
Preferably, the synthesis processing unit synthesizes the layout module and/or obtains a geometrical function parameterized by delay for the layout module.
This enables the synthesis processing unit to obtain a geometrical function parameterized by delay for the layout module, so that a linkage to the upper process of design is established more easily as compared with a conventional apparatus.
The present invention also provides a module synthesizing apparatus for synthesizing a layout module for a data path circuit, including: a data-path-diagram display correcting unit for displaying a data path diagram and for correcting an arrangement of registers in the data path diagram based on an instruction given from the outside of the module synthesizing apparatus; a function-property estimating unit for estimating a delay in each of functions of the data path diagram; and a function-property display unit for displaying the delay in each said function estimated by the function-property estimating unit.
According to the present invention, a user can interactively correct the arrangement of registers in the data path diagram by using the data-path-diagram display correcting unit, while monitoring the delay in the function displayed by the function-property display unit. This facilitates the correction of imbalanced processing times in the individual time slots and allows the synthesis of a module more excellent in delay performance as compared with a conventional apparatus.
The present invention also provides a module synthesizing method for synthesizing a layout module for a data path circuit, including the steps of: converting a data path diagram into logic circuit data representing the data path circuit on a logic level by allocating a logic circuit to each function; specifying cells in the data path circuit based on the logic circuit data; obtaining a geometrical function parameterized by delay for each of the specified cells; and synthesizing a layout module based on a floorplan for the layout module and the geometrical functions of the cells which have been parameterized by delays.
Preferably, the module synthesizing method further includes a step of synthesizing the layout module and/or obtaining a geometrical function parameterized by delay for the layout module.
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J. Cong, et al., 'General Models and Algorithms For Over-The-Cell Routing in Standard Cell Design, Proc. of 27thACM/IEEE
Do Thuan
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
Smith Matthew
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