Apparatus and method for synchronizing multiple threads in...

Details Apparatus and method for synchronizing multiple threads in... Apparatus and method for synchronizing multiple threads in...

2003-05-01

2009-02-17

An, Meng-Ai (Department: 2195)

Electrical computers and digital processing systems: virtual mac

Task management or control

C712S234000

Reexamination Certificate

active

07493615

ABSTRACT:
The present invention generally relates to synchronization of multiple threads in an out-of-order microprocessor utilizing the insertion of a trap. In one embodiment, while synchronizing multiple running threads, an instruction within a first running thread is identified. Upon identification of this instruction, a trap is inserted into a second running thread. All instructions within the instructional pipeline that are scheduled for execution prior to this trapped instruction must retire before the subsequent execution of the synchronizing instruction. Following the execution of the synchronizing instruction, all instructions within the instruction pipeline slated for execution after the trapped instruction in the remaining threads are flushed and refetched.

REFERENCES:
patent: 5357617 (1994-10-01), Davis et al.
patent: 5797004 (1998-08-01), Lindholm et al.
patent: 6718484 (2004-04-01), Kodera
patent: 2001/0044892 (2001-11-01), Yamaura
patent: 2003/0061258 (2003-03-01), Rodgers et al.
patent: 2004/0210876 (2004-10-01), Stall et al.

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