Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1996-06-28
2001-08-21
Gossage, Glen (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S162000, C711S165000, C714S006130, C714S012000, C714S015000, C714S042000
Reexamination Certificate
active
06279078
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
This invention relates to synchronizing dual controllers in a cache memory system having two cache modules. More particularly, the invention relates to synchronizing the controllers whereby the controllers may control mirror and non-mirror writes to the cache modules and preventing one controller from improperly accessing a cache module under control of the other controller.
2. Description of Related Art
To date, cache memory systems where there is a mirror write operation have used two separate memory caches and written the data word, or block, first in one cache, read it from that cache and mirror-written it to the second cache. The advantage of writing a data word to two separate cache modules is the greatly enhanced reliability of the cache memory system. Such a mirror cache system carries the penalty, of course, that if each word unit is written twice, the capacity of the cache memory system is effectively cut in half.
There may be situations where the mirroring of data in two cache modules is not required. For example, if the data is only to be read, it is not necessary to write such data from main memory to two cache modules. This is true because if the data is lost from the cache module where it is written, it may be recovered from main memory. Also, users of the system may opt to have greater cache capacity rather than to mirror write data in two cache modules. Accordingly it is desirable to operate in both a mirror cache mode and a non-mirror cache mode in a dual cache module system.
In a dual controller, dual cache system there is a need to control the access of each controller to each cache module. It is important to prevent one controller from accessing the cache modules improperly if the controller malfunctions. Further, the control functions are needed in both a mirror cache mode and a non-mirror cache mode.
SUMMARY OF THE INVENTION
In accordance with this invention, the above problem has been solved by controlling accesses between controllers and cache modules in a cache memory system in a computer. The cache memory system has two controllers and two cache modules and operates in a non-mirror cache mode and a mirror cache mode. Data indicating the cache mode to be used is stored as metadata in the cache modules. The metadata in the cache modules is detected to determine the cache mode. Lock signals in one of the controllers are set in accordance with the cache mode to set the cache mode state of the controller. The cache mode state being mirror or non-mirror state. The other controller copies the lock state from the first controller to synchronize both controllers in the same cache mode state.
In another feature of the invention one of the controllers acts as a surviving controller detecting that the other controller is a failed controller. The surviving controller locks access to both cache modules to recover data previously accessed by the failed controller. The surviving controller runs in the cache mode state of the cache mode prior to failure of the failed controller. The failed controller starts-up so that it is a restarted failed controller. The lock state of the surviving controller is copied by the restarted failed controller whereby the controllers return to a lock state in the cache mode existing prior to failure of the restarted failed controller.
As another feature of the invention one controller detects that the cache mode has changed from an old mode to a new mode. This controller sets the lock signals so that it is in a lock state corresponding to the new mode. The other controller copies the lock signals so that it is in the new lock state corresponding to the new mode.
The great advantage and utility of the present invention is the control of access, synchronization and direction of error messages in the dual controller, dual cache system.
The foregoing and other features, utilities and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention as illustrated in the accompanying drawings.
REFERENCES:
patent: 5437022 (1995-07-01), Beardsley et al.
patent: 5479413 (1995-12-01), Sicola et al.
patent: 5544347 (1996-08-01), Yanai et al.
patent: 5553263 (1996-09-01), Kalish et al.
patent: 5574863 (1996-11-01), Nelson et al.
patent: 5588110 (1996-12-01), DeKoning et al.
Elkington Susan G.
Lubbers Clark E.
Sicola Stephen J.
Umland Wayne H.
Compaq Computer Corporation
Gossage Glen
Hogan & Hartson LLP
Hudgens Ronald C.
Kubida William J.
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