Apparatus and method for switching threads in...

Electrical computers and digital processing systems: processing – Processing control – Context preserving (e.g. – context swapping – checkpointing,...

Reexamination Certificate

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C712S043000, C712S215000, C712S229000

Reexamination Certificate

active

07421571

ABSTRACT:
A multi-threaded processor is provided. The multi-threading processor includes a first instruction fetch unit and a second instruction fetch unit. A multi-thread scheduler unit is coupled to the first instruction fetch unit and the second instruction fetch unit. An execution unit, which executes a first active thread and a second active thread is coupled to the scheduler unit. The multi-threading processor also includes a register file coupled to the execution unit. The register file switches one of the first active thread and the second active threads with a first inactive thread.

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Susan J. Eggers, Simultaneous Multithreading: A Platform for Next-Generation Processors, 1997 IEEE Micro, pp. 12-19.
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Oehring, H.;Sigmund, U;Ungerer, T., “MPEG-2 video decompression on simulaneous multithreaded multimedia processors,” Parallel Architectures and Compilation Techniques, 1999, IEEE proceedings, pp. 11-16.
Eggers, Susan, et al., Simultaneous Multithreading: A platform for Next-Generation Processors, Sep./Oct. 1997 IEEE Micro, pp. 12-19.

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