Electrical computers and digital processing systems: processing – Processing control – Context preserving (e.g. – context swapping – checkpointing,...
Reexamination Certificate
2006-11-07
2006-11-07
Fleming, Fritz (Department: 2181)
Electrical computers and digital processing systems: processing
Processing control
Context preserving (e.g., context swapping, checkpointing,...
C712S229000, C712S043000, C712S215000
Reexamination Certificate
active
07134002
ABSTRACT:
An multi-threading processor is provided. The multi-threading processor includes a first instruction fetch unit and a second instruction fetch unit. A multi-thread scheduler unit is coupled to the first instruction fetch unit and the second instruction fetch unit. An execution unit, which executes a first active thread and a second active thread is coupled to the scheduler unit. The multi-threading processor also includes a register file coupled to the execution unit. The register file switches one of the first active thread and the second active threads with a first inactive thread.
REFERENCES:
Eggers, Susan, et al., Simultaneous Multithreading: A Platform for Next-Generation Processors, Sep./Oct. 1997, IEEE Micro, pp. 12-19.
Ungerer, et al., Multithreaded processors, 2002, British Computer Society, The Computer Journal, vol. 45, No. 3, pp. 320-348.
Oehring, H.; Sigmund, U.; Ungerer, T., “MPEG-2 video decompression on simultaneous multithreaded multimedia processors,” Parallel Architectures and Compilation Techniques, 1999, IEEE Proceedings, pp. 11-16.
Fleming Fritz
Meonske Tonia L.
Steiner Paul E.
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