Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1997-08-28
2001-02-13
Thai, Tuan V. (Department: 2752)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S100000, C365S218000, C365S042000, C710S048000, C710S260000
Reexamination Certificate
active
06189070
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of memory devices. More particularly, this invention relates to suspending an operation in a nonvolatile writeable memory in order to perform other operations in the nonvolatile writeable memory.
BACKGROUND OF THE INVENTION
One type of prior art nonvolatile writeable memory is a flash device. A typical flash device has the same array configuration as a standard Electrically Programmable Read-Only Memory (“EPROM”) and can be programmed in a similar fashion as an EPROM. Once programmed, either the entire contents of the flash device or a block of the flash device can be erased by electrical erasure in one relatively rapid operation. An erasing voltage is made available to the sources of all the cells in the flash device or in one block of the flash device. This results in a full array erasure or a block erasure. The flash device or the erased block of the flash device may then be reprogrammed with new data.
Flash devices may be read, programmed (or written), and erased. For a prior art flash device, a program operation to write a byte of data typically takes on the order of 10 microseconds. Because, however, there is some margin required for guaranteeing that the program operation has properly completed, a maximum program time is specified by the flash device manufacturer. Thus, while the typical program operation may take 10 microseconds, the system may need to wait a maximum program operation time of 100 microseconds in order to guarantee that the program operation performed correctly.
Similarly, for a prior art flash device, an erase operation may take from 300-600 milliseconds in order to erase a 8 kilobyte block of data. However, the flash device may require up to a maximum erase operation time of 3 seconds in order to guarantee that the erase operation of the entire block of data has performed correctly.
Because the erase operation has such a long latency time, a prior art flash device includes an erase suspend command. When an erase suspend command is written to the flash device, the flash device suspends the erase operation that is being performed. Other operations may then be performed on the flash device. Subsequently, when an erase resume command is written to the flash device, the flash device resumes the erase operation from where it was suspended. An implementation of the erase suspend circuitry is described in U.S. Pat. No. 5,355,464, entitled “Circuitry And Method For Suspending The Automated Erasure Of A Non-Volatile Semiconductor Memory,” by Fandrich et al., and issued to the common assignee of this application.
FIG. 1
shows a prior art representation of a system comprising a processor
100
, a volatile memory
102
, and a flash device
104
coupled together via a bus
108
. The volatile memory
102
and the flash device
104
, however, could be coupled to the processor
100
, via separate buses. The flash device includes a memory array for storing both code and data, wherein the code is executable by the processor.
A problem occurs in this configuration when an interrupt causes the processor
100
to autovector, i.e., automatically vector execution in response to the interrupt, to an interrupt handler located within the flash device or normal code execution attempts to execute from the flash. A typical flash device has at least two modes—a read mode and a status mode in addition to other modes. In one prior art flash device, the flash device transitions into status mode automatically when a program or an erase operation is performed. The flash device remains in status mode until the flash device finishes its non-read operation. If a read is performed during this time, status of the flash device is returned indicating whether the non-read operation has completed. In order to subsequently read data (or code) from the flash device, the flash device is changed back to its read mode by writing to a register within the flash device. Thus, if an interrupt causes the processor to read from the flash device while the flash device is still in status mode, the processor will not read the code that it is expecting—it will instead read status. (In the following discussion, “code” is used to denote bits which are executable by a processor, and “data” is used to denote bits which are not executable by a processor.)
One solution is to shadow, or copy, the code from the flash device to the volatile memory, which is typically either dynamic random access memory (DRAM) or static random access memory (SRAM). After the code is shadowed in the volatile memory, if the flash device is performing a program operation and the processor generates a code fetch request due to an interrupt, for example, then the processor can satisfy the code fetch request by reading the requested code from the volatile memory
102
. The processor does not need to wait for the flash device
104
to finish its program operation in order to perform the code fetch.
This scheme, however, may be expensive if the size of the code stored in the flash device is large, since the DRAM/SRAM would need to be large enough to store the entire code block in order to overcome the program operation latency. This scheme also requires the microprocessor to have a capability to “re-vector” its interrupts to RAM. Most microprocessors do not have this capability.
FIG. 2
shows an example of a prior art system which utilizes a fixed hardware partition
110
within the flash device
104
to separate the code from the data. Extra circuitry is added to the flash device to allow only a data section to enter status mode while a code section remains in read mode. Atypical approach is to partition the memory on a block boundary and then duplicate memory array row and column decoders, and charge pump circuits. The duplicate circuitry is needed to segment the standard memory array into separate physical partitions which can be sensed separately. Thus, when the data partition status is busy (e.g., array cells are being programmed or erased), the code partition has row/column decode circuitry available for reading.
However, the extra circuitry is expensive and increases the die size of the flash device. Additionally, the fixed sizes of the data section and the code section created by the hardware partition
110
restrict the flexibility of usage of the flash device.
SUMMARY OF THE PRESENT INVENTION
A method and apparatus for managing data and reading of code from a nonvolatile writeable memory is described. The nonvolatile writeable memory stores both code and data. In a nonvolatile writeable system, interrupts are disabled. A non-read operation is initiated in the nonvolatile writeable memory. A check for whether an interrupt has occurred is performed. If an interrupt has occurred, then the non-read operation in the nonvolatile writeable memory is suspended. Interrupts are enabled, and code is read from the nonvolatile writeable memory. Non-read operations may include program operations and erase operations.
Other features, and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.
REFERENCES:
patent: 4965828 (1990-10-01), Ergott et al.
patent: 5021996 (1991-06-01), Watanabe
patent: 5255314 (1993-10-01), Applegate et al.
patent: 5287469 (1994-02-01), Tsuboi
patent: 5351216 (1994-09-01), Salt et al.
patent: 5355464 (1994-10-01), Fandrich et al.
patent: 5369754 (1994-11-01), Fandrich et al.
patent: 5377145 (1994-12-01), Kynett et al.
patent: 5414829 (1995-05-01), Fandrich et al.
patent: 5418752 (1995-05-01), Harari et al.
patent: 5422843 (1995-06-01), Yamada
patent: 5424992 (1995-06-01), Coffman et al.
patent: 5424993 (1995-06-01), Lee et al.
patent: 5521864 (1996-05-01), Kobayashi et al.
patent: 5568644 (1996-10-01), Nelson et al.
patent: 5590073 (1996-12-01), Arakawa
patent: 5687121 (1997-11-01), Lee et al.
patent: 5742787 (1998-04-01), Talreja
patent: 5805929 (1998-09-01), Connolly et al.
Hasbun Robert N.
See Deborah L.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Thai Tuan V.
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