Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-04-01
2010-11-23
Bragdon, Reginald G (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S213000, C711SE12004, C711SE12057, C712S207000, C712S029000
Reexamination Certificate
active
07840761
ABSTRACT:
A processor executes one or more prefetch threads and one or more main computing threads. Each prefetch thread executes instructions ahead of a main computing thread to retrieve data for the main computing thread, such as data that the main computing thread may use in the immediate future. Data is retrieved for the prefetch thread and stored in a memory, such as data fetched from an external memory and stored in a buffer. A prefetch controller determines whether the memory is full. If the memory is full, a cache controller stalls at least one prefetch thread. The stall may continue until at least some of the data is transferred from the memory to a cache for use by at least one main computing thread. The stalled prefetch thread or threads are then reactivated.
REFERENCES:
patent: 6134633 (2000-10-01), Jacobs
patent: 2002/0194354 (2002-12-01), Bolduc et al.
patent: 2004/0098552 (2004-05-01), Kadi
patent: 2004/0215921 (2004-10-01), Alexander et al.
Colavin Osvaldo M.
Rizzo Davide
Bragdon Reginald G
Jorgenson Lisa K.
Loonan Eric
Munck William A.
STMicroelectronics Inc.
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