Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2000-06-09
2004-03-30
Bataille, Pierre-Michel (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S170000, C360S048000
Reexamination Certificate
active
06715030
ABSTRACT:
FIELD OF THE INVENTION
The present invention is directed to an apparatus and method for storing track layout information for performing update write operations. In particular, the present invention is directed to an apparatus and method for storing track layout information based on disk cylinders which is then used to verify a quick write operation.
BACKGROUND OF THE INVENTION
Use of Direct Access Storage Devices (DASDs) in a data processing system requires performance of certain Input/Output (I/O) functions. Data must be transferred between the DASD and the host processor. Such DASDs are often connected to a host processor through an I/O channel. The host Central Processing Unit (CPU) operating system initiates data transfer with a command to the I/O channel. This shifts control to a series of Channel Command Words (CCWs) that are sent from the CPU over the channel to the DASD controller for effectuating data movement across the interface.
The channel forwards each CCW to the controller for a selected DASD. Once the channel passes a command to a particular controller, the command must be interpreted and the elements of the command must be executed by the DASD. The various functions of channel, controller and command interpretation can be integrated with the host processor or distributed between the host and the mechanical storage components of the DASD.
The DASD controller performs several functions, including the interpretation and execution of CCWs forwarded by a channel from the host CPU. Seek commands position a DASD access mechanism. Search commands cause comparison between data from main CPU storage and data stored on specified DASD areas. Read commands cause data copies to be transferred from DASD storage to main CPU storage and checked for validity.
Another important function of the DASD controller is the prescription of data storage format for the DASD. Such a format includes provisions for certain “non-data” information such as the track address, record address, and so forth. There are also unused spaces and error correction codes prescribed for the DASDs commonly encountered in widespread use.
Conventional track formats include an index point on each track of the recording surface indicating the physical beginning of the track. Also, on each track, there is normally one Home Address (HA) that defines the physical location of the track and the condition of the track. The HA normally contains the physical track address, a track condition flag, a cylinder number (CC) and a head number (HH). The combination of the cylinder number and head number indicates the track address and is commonly expressed in the form CCHH. The HA contains the “physical” track address, which is distinguished from a “logical” track address. The physical and logical track addresses may differ for records stored in the DASD tracks.
The first record following the HA is commonly a track descriptor record, sometimes referred to as R
0
. One or more user data records follow R
0
on the track. The first part of each user record is an “address marker” that enables the controller to locate the beginning of the record when reading data from DASD. Each user record is commonly formatted in either a “count-data” (CD) or a “count-key-data” (CKD) format. The only difference between the CD and CKD formats is the presence of key fields and key length data in the CKD formatted record. Both are herein henceforth referred to as CKD records.
The CKD record consists of a count field, an optional key field and a variable-length data field. The typical count field is of the form CC (two bytes of cylinder number), HH (two bytes of head number), R (one byte of record number), KL (one byte of key length), and DL (two bytes of data length). Thus, each CKD record is self-identifying. The CCHH in the count field (called “logical” CCHH) is typically the same as the cylinder and head numbers in the HA for the track containing the record (called “physical” CCHH), although not necessarily. Thus, a CKD track consists of the track header (HA and R
0
) followed by some number of CKD records. The CKD record numbers (R) may, but need not, increment along the track in a monotonic pattern of one, two, three, and so on.
In the typical situation, user data is written or read in a data field of a CKD record in some track on some DASD. The channel specifies the device and the track within the device of interest. The channel may also specify the rotational position on the track from which to begin searching for the record having the data field to be read or written. This is accomplished by specifying a search parameter (five bytes in the form CCHHR) for use by the DASD controller to match against count fields in the track of interest. When the DASD controller finds a CKD record on the track with a count field that matches the search parameter, it then either reads or writes the corresponding data field.
The fundamental feature of importance to this invention is that the disk controller is not permitted to read or write until it has verified the existence of a count field in the track that matches the channel search parameter. This means that a write command will force the channel to wait until the matching record is actually located on the rotating DASD medium. Of course, such a read wait state is reasonable because a CKD record cannot be read until located, but the only overriding reason for holding the CPU channel merely to locate the proper record for updating is to ensure error recovery.
The prior art is replete with methods for reducing and eliminating the host CPU wait states necessitated by DASD accesses for read and write. A DASD cache is a high-speed buffer store used to hold portions of the DASD address space contents in a manner that reduces channel wait states. U.S. Pat. No. 4,603,380 discloses a method for DASD cache management that reduces the volume of database transfers between DASD and cache, while avoiding the complexity of managing variable length records in the cache. This is achieved by forcing the starting point for staging a record to the beginning of the missing record and, at the same time, allocating and managing cache space in fixed length blocks.
Some DASD controllers such as the IBM 3990 DASD controller, have some amount of relatively fast Non-Volatile Store (NVS) for storing records that have been written by the host system but not yet written to the DASD medium by the DASD controller. The NVS is additional to the high speed cache buffer store commonly included in the typical disk controller. DASD controllers having both cache and NVS are said to perform “fast-write” operations.
A fast-write operation proceeds as follows, if a track record to be updated is already in cache (that is, a record count field is found in cache that matches the search parameters provided by the host computer), the cache copy of the record is updated in cache and another updated copy is made in NVS. The two copies of modified records are maintained for error recovery purposes to avoid single points of failure. After copying to NVS, the DASD controller returns a completion signal to the host system, freeing the host CPU to proceed with the next channel operation. Such an operation is called a “fast-write hit” and is completed well before the updated record is actually written to the DASD. At some later time, the DASD controller asynchronously de-stages the updated record to disk from the cache and then removes the record from NVS and optionally cache as well.
This explanation, made in terms of a single record, actually is better understood in terms of a single track. DASD controller cache memory is generally organized in fixed block sizes. Because a single track is often a fixed size while single records are not, the typical practice is to stage and de-stage data from cache to DASD and back again in single track increments.
With a “fast-write hit”, the DASD controller can eliminate the disk access time from the channel write operation as perceived by the host CPU. The actual de-stage of the modified record from cache to disk can be ac
Milillo Michael Steven
Peterson Gregory William
Vandenbergh Henk
Bataille Pierre-Michel
Carstens Yee & Cahoon LLP
Storage Technology Corporation
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