Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
1998-06-05
2001-03-06
Thai, Tuan V. (Department: 2752)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S205000, C711S206000
Reexamination Certificate
active
06199151
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to virtual addressing, and more particularly to reducing the amount of time required to access memory in response to a virtual address reference.
BACKGROUND OF THE INVENTION
Many modern computer systems use virtual addressing to hide the underlying complexity of their physical address spaces. A virtual address is an address that must be translated into a physical address before it can be used to access memory. By presenting a computer system's operating memory as a virtual address space, the operating memory may be made to appear larger or less fragmented than it actually is. For example, in a computer system that has a 32 MB (mega-byte) operating memory, an even larger virtual memory may be presented for use by application programs by mapping portions of the virtual memory to a storage other than the operating memory (e.g., a disk drive). If necessary, regions of the virtual address space can be dynamically remapped from a relatively slow mass storage device to operating memory. Also, a physical operating memory that has gaps of unused physical address space (i.e., a fragmented memory) can be made to appear as a contiguous address space in the virtual realm.
One important application of virtual addressing is the storage and retrieval of graphics objects, such as textures, depth information and color information, in operating memory. Because graphics objects are often used to provide real-time visual effects, it is important that graphics objects be retrieved from memory quickly and without spending excessive time translating their virtual address references.
In many computer systems, virtual addresses are translated into physical addresses by a processor (or other bus master) before the processor issues memory access requests to a memory controller. In other computer systems, at least some virtual-to-physical address translation is performed in the memory controller. Performing address translation in the memory controller centralizes the address translation activity and allows virtual addressing to be used by subsystems in the computer system that do not have address translation capability.
One technique for performing virtual-to-physical address translation in a memory controller is to use a translation buffer in conjunction with a lookup table in memory. If a virtual address is received in the memory controller, the memory controller checks to see if a corresponding physical address is stored in the translation buffer (a translation buffer hit). If so, the physical address is output from the translation buffer and used to access memory. If the physical address is not stored in the translation buffer (a translation buffer miss), the physical address is retrieved from the lookup table in memory. The physical address from the lookup table is used to access memory and is also written to the translation buffer to increase the likelihood of a subsequent translation buffer hit.
After a physical address is obtained in a memory controller, the physical address must still be decoded in order to produce the signals necessary to access memory. One decoding operation that must be performed is the decoding of a physical address into one or more signals for selecting a memory device (or group of devices) that is mapped to the memory location sought to be accessed. This decoding operation is commonly referred to as a row decode operation because memories are often organized in rows of devices (“device rows”), with each device row being selectable independently of the other device rows.
Unfortunately, due to cumulative propagation delays inherent in a row decoding operation, row decoding usually takes relatively long time. This is significant because the row decode operation occurs after virtual-to-physical address translation is completed and therefore directly impacts the overall memory access time. Consequently, any reduction in the time required to select a device row in response to a virtual address tends to reduce memory access time and increase the overall performance of the computer system.
SUMMARY OF THE INVENTION
An apparatus and method for selecting a row of memory devices are disclosed. A row value that indicates one of a number of chip select signals is stored in a storage element that is associated with an address . A memory access request that includes the address is received, and the chip select signal indicated by the row value is asserted to select one of a number of rows of memory devices.
Other features and advantages of the invention will be apparent from the accompanying drawings and from the detailed description that follows below.
REFERENCES:
patent: 5134582 (1992-07-01), Ishii
patent: 5479635 (1995-12-01), Kametani
patent: 5500948 (1996-03-01), Hinton et al.
patent: 5517634 (1996-05-01), Ehrlich
patent: 5630087 (1997-05-01), Talluri et al.
Hunsaker Mikal
Murdoch Robert N.
Raderman Leslie
Williams Michael W.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Raderman Leslie
Thai Tuan V.
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