Apparatus and method for speeding up access time of a large...

Details Apparatus and method for speeding up access time of a large... Apparatus and method for speeding up access time of a large...

2007-07-10

2007-07-10

Portka, Gary (Department: 2188)

Electrical computers and digital processing systems: memory

Address formation

Address multiplexing or address bus manipulation

C711S217000, C711S218000, C711S219000, C365S230020

Reexamination Certificate

active

11044449

ABSTRACT:
An apparatus and method for speeding up access time of a large register file with wrap capability are provided. With the apparatus and method, the 2:1 multiplexers in conventional register file systems are eliminated from the circuit configuration and instead, additional primary multiplexers are provided for half of the addresses, e.g., the first four sub-arrays of the register file for which the wrap capability is needed. These additional primary multiplexers receive the read address and a shifted read word line signal. The other primary multiplexer receives the read address and an unshifted read word line signal. The outputs from the shifted and non-shifted primary multiplexers are provided to a set of secondary multiplexers which multiplex bits from the outputs of the shifted and non-shifted primary multiplexers to generate the read addresses to be used by the multiple read/write register file system.

REFERENCES:
patent: 5005120 (1991-04-01), Ruetz
patent: 6002880 (1999-12-01), Slavenburg
patent: 6662261 (2003-12-01), Duboc et al.
patent: 6721295 (2004-04-01), Brown
patent: 2002/0122443 (2002-09-01), Enam et al.
patent: 2004/0039898 (2004-02-01), Bosshart
patent: 2004/0252728 (2004-12-01), Rose

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