Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-04-18
2003-01-14
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C327S099000, C702S117000
Reexamination Certificate
active
06507934
ABSTRACT:
BACKGROUND
Manufacturers of integrated circuits need to verify that chips do indeed meet design specifications and are suitable for board installation and customer delivery. Two significant parameters of chips are setup time and hold time.
However, the technology of chip design outpaces the technology of testers. Testers lack sufficient resolution to adequately test high speed, state of the art chips. In response, many chips include self-testing circuitry. Various protocols embedded into a chip exist for testing the chip and verifying that the chip meets design specifications. Existing protocols include protocols to test internal circuitry of the chip, and protocols to test the interconnects between chips, such as Interconnect BIST. However, testing setup and hold times remains problematic for high-speed chips.
One way of testing setup and hold times for high speed chips includes the use of source synchronous links. A source synchronous link sends data bits together with a clock signal from a transmitter to a receiver, such as chip to chip. Source synchronous links allow faster chip operation. Setup time and hold time can be tested with a source synchronous link between chips by altering the propagation delays or durations of links carrying data relative to a propagation delay or duration of a link carrying the clock signal, or by altering the duration of the link carrying the clock signal relative to the duration of links carrying data. This approach, however, can be difficult to implement, and have inaccurate results.
Additionally, skew increases the difficulty in correctly testing the setup and hold times. Skew is the difference in propagation delay between two signals transiting different links, caused by manufacturing difficulties in constructing two links to behave precisely the same. Thus, a manufacturer could prematurely rate a given chip as having met specifications, when skew could mean that only some links actually passed.
To be economical, setup and hold times of chips need to be tested very rapidly. Moreover, manufacturers may find it helpful if chips failing to meet setup and/or hold time specifications can be further tested to measure just how closely the failing chips came to meeting the setup and hold time specifications. Further, testing of setup and hold specifications should be scalable, so that the solution can keep pace with increasing chip speeds.
SUMMARY
To overcome the limitations described above, and to overcome other limitations that will become apparent upon reading and understanding the present specification, the present invention discloses an improved circuit board for use in systems that test chips for compliance with setup and/or hold time specifications. It is one object of the invention to provide a circuit board having a first chip, and a second chip to be tested coupled to the first chip, with multiple links of different lengths for testing the setup time and/or hold time of the second chip. It is another object of the invention to test skew within a bus. It is a further object of the invention to not only test whether the second chip met specifications for setup time and/or hold time, but also test how much the second chip exceeded or failed specifications.
In accordance with these objects, the present invention includes a circuit board comprising a first chip, a second chip, and a plurality of links coupling the first chip and the second chip. A first link carries a clock signal between the first chip and the second chip; the clock signal takes a first duration to transit the first link. A second link is associated with a second duration for data transiting the second link. The shorter the second duration relative to the first duration, the earlier the data transiting the second link arrives at the second chip, relative to the clock signal transiting the first link arriving at the second chip. The longer the second duration relative to the first duration, the later the data transiting the second link arrives at the second chip, relative to the clock signal.
In one embodiment, the plurality of links includes at least one link for carrying data to test a setup time of a second chip, and at least one link for carrying data to test a hold time of the second chip. After the data arrives at the second chip, the data are checked to verify that the setup and the hold times of the second chip are adequate.
The present invention is also scalable for future processors with shorter setup and hold times; the setup and hold time specifications may be tested after appropriately adjusting the lengths of the plurality of links coupling the first and second chips.
REFERENCES:
patent: 5650734 (1997-07-01), Chu et al.
patent: 5742188 (1998-04-01), Jiang et al.
patent: 6133751 (2000-10-01), Churcher et al.
patent: 6324485 (2001-11-01), Ellis
Rossoshek Helen B
Siek Vuthe
Sun Microsystems Inc.
Sun Microsystems, Inc.
Suzue Kenta
LandOfFree
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