Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-03-28
2006-03-28
Kim, Hong (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S145000, C711S146000, C711S131000, C711S154000, C713S600000
Reexamination Certificate
active
07020752
ABSTRACT:
In a data cache unit that exchanges data signal groups with at least two execution units, the operation of the data cache unit is implemented as a three-stage pipeline in order to access data at the speed of the system clock. The data cache unit has a plurality of storage cell banks. Each storage cell bank has valid bit array unit and a tag unit for each execution unit incorporated therein. Each valid bit array unit has a valid/invalid storage cell associated with each data group stored in the storage cell bank. The valid bit array units have a read/write address port and snoop address port. During a read operation, the associated valid/invalid signal is retrieved to determine whether the data signal group should be processed by the associated execution unit. In a write operation, a valid bit is set in the valid/invalid bit location(s) associated with the storage of a data signal group (or groups) during memory access. The valid bit array unit responds to a snoop address and a control signal from the tag unit to set an invalid bit in a valid/invalid bit address location associated with the snoop address. The tag unit can be divided into a plurality of tag subunits to expedite processing.
REFERENCES:
patent: 5319768 (1994-06-01), Rastegar
patent: 5471637 (1995-11-01), Pawlowski et al.
patent: 5553266 (1996-09-01), Metzger et al.
patent: 5598550 (1997-01-01), Shen et al.
patent: 5829032 (1998-10-01), Komuro et al.
patent: 6430658 (2002-08-01), Nunez et al.
patent: 6453387 (2002-09-01), Lozano
patent: 6460133 (2002-10-01), Nunez et al.
patent: 6675266 (2004-01-01), Quach et al.
patent: 2004/0153598 (2004-08-01), Thatipelli et al.
Thatipelli Krishna M.
Tzeng Allan
Hamilton & Terrile LLP
Kim Hong
Sun Microsystems Inc.
Terrile Stephen A.
LandOfFree
Apparatus and method for snoop access in a dual access,... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and method for snoop access in a dual access,..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for snoop access in a dual access,... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3609658