Electrical computers and digital processing systems: processing – Processing control – Arithmetic operation instruction processing
Reexamination Certificate
1998-07-15
2001-05-01
Treat, William M. (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Arithmetic operation instruction processing
C708S501000, C708S503000
Reexamination Certificate
active
06226737
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to the field of data processing in computers, and more particularly to an apparatus and method for multiplying single precision binary operands.
2. Description of the Related Art
Software programs that execute on a microprocessor consist of macro instructions that together direct the microprocessor to perform a function. Each macro instruction directs the microprocessor to perform a specific operation that is part of the function such as loading data from memory, storing data in a register, or adding the contents of two registers.
A macro instruction may prescribe a simple operation, such as moving the contents of one register location to another register location. In contrast, a different macro instruction may prescribe a complex operation, such as deriving the cosine of a floating point number. Compared to the manipulation of integer data, the manipulation of floating point data by the microprocessor is complex and time consuming. Movement of integer data requires only a few cycles of a microprocessor clock; derivation of a cosine requires hundreds of machine cycles. Because floating point operations are basically more complex than integer operations, typical microprocessors employ a dedicated floating point unit to improve the speed and efficiency of floating point calculations. The dedicated floating point unit may be part of the same mechanical package as the remainder of the microprocessor or it may reside in a separate mechanical package.
Within an ×86-compatible microprocessor, a floating point macro instruction is decoded into a sequence of floating point micro instructions that direct the microprocessor to execute a floating point operation. The sequence of floating point micro instructions is passed to the floating point unit. The floating point unit executes the sequence of floating point micro instructions and provides a result of the floating point operation in a result register. Likewise, an integer macro instruction is decoded into a sequence of integer micro instructions that direct the microprocessor to execute an integer operation. The sequence of integer micro instructions is passed to the integer unit. The integer unit executes the sequence of integer micro instructions and provides a result of the integer operation in a result register.
In recent years, desktop computational demands have placed a greater burden upon microprocessor designers to add increasingly more functionality to a microprocessor's instruction set. In fact, floating point operations are so common now that a vast majority of present day floating point units perform their computations on operands which adhere to industry standard extended precision format. A number in extended precision format has a 64-bit significand. To implement extended precision capability in a floating point unit essentially requires adding more logic circuits to a device. But the additional logic results in a greater power requirement, which is inversely proportional to device reliability. Consequently, microprocessor designers are now searching for alternative ways to add functions to a device. Designers now use existing logic to perform new functions, or they eliminate redundant logic and redistribute existing functions to remaining logic. One example of an alternative is seen in the implementation of logic to perform floating point multiplication.
A basic floating point multiplication unit multiplies a 64-bit multiplicand by a 64-bit multiplier. Recognizing the benefits inherent in reducing the size of the multiplication unit, microprocessor designers today provide multiplication units on the order of 64-bits by 32-bits. These are commonly called dual pass multiplication units. A lower half of the multiplier in a first pass is multiplied with the multiplicand to form a first partial product. Following this, an upper half of the multiplier in a second pass is multiplied with the multiplicand to form a second partial product. The second partial product is left-shifted accordingly and summed with the first partial product to yield a final product. By such an implementation, the logic requirements for extended precision multiplication are roughly halved with only a slight increase in the number of machine cycles required to compute a product.
Yet, there are a significant number of extant software applications for which single precision multiplication is sufficient. A single precision number comprises a 24-bit significand. When a single precision number is provided to an extended precision floating point unit, it is translated into extended precision format. But this translation results in the lower 40 bits of its significand being equal to zero. Hence, multiplication of a single precision number in a dual pass multiplication unit will take two passes, but, the first pass is essentially wasted because it is consumed multiplying a 64-bit multiplicand by zero.
Therefore, what is needed is an apparatus for performing single precision multiplication in a microprocessor faster than has heretofore been provided.
In addition, what is needed is a microprocessor that executes a single precision multiplication that requires only one pass through a dual pass multiplication unit.
Furthermore, what is needed is a method for performing single precision multiplication in a microprocessor that eliminates unnecessary clock cycles associated with the performance of extended precision multiplication.
SUMMARY
To address the above-detailed deficiencies, it is an object of the present invention to provide an apparatus in a microprocessor that performs single precision multiplication faster than conventional dual pass multiplication units.
Accordingly, in the attainment of the aforementioned object, it is a feature of the present invention to provide a microprocessor for performing single precision floating point multiplication of a multiplicand by a multiplier, where the multiplicand and the multiplier are provided in extended precision format. The microprocessor includes a translator and extended precision floating point execution logic. The translator receives a single precision multiplication instruction, and decodes the single precision multiplication instruction into an associated single precision micro instruction sequence. The extended precision floating point execution logic is coupled to the translator. The extended precision floating point execution logic receives the associated single precision micro instruction sequence, and multiplies the multiplicand by the multiplier to generate a single precision product. The extended precision floating point execution logic normally performs a floating point multiplication by generating a low-order partial product followed by generation of a high-order partial product, where the low-order partial product represents multiplication of a low-order part of an extended precision multiplier with an extended precision multiplicand, and where the high-order partial product represents multiplication of a high-order part of the extended precision multiplier with the extended precision multiplicand The low-order partial product is generated during a first traversal through the extended precision floating point execution logic, and the high-order partial product is generated during a second traversal through the extended precision floating point execution logic. When the associated single precision micro instruction sequence is received, the extended precision floating point execution logic generates the single precision product by executing only the second traversal to generate the high-order partial product, the high-order partial product being the single precision product.
An advantage of the present invention is that single precision multiplication requires roughly half of the execution time of extended precision multiplication.
Another object of the present invention is to provide a microprocessor that executes a single precision multiplication without requiring two passes through a dual pass mult
Elliott Timothy A.
Henry G. Glenn
Huffman James W.
Huffman Richard K.
IP-First L.L.C.
Treat William M.
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