Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-11-08
2003-11-11
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06647538
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention is directed generally toward the measuring of signal skew between two on-chip signals to identify operational characteristics of circuit components. More specifically, the present invention is directed toward the characterization of signal skew using clock division.
2. Description of the Related Art
Measurement of signal skew is important in verifying simulation data to determine if computer simulations of circuit designs accurately reflect the resultant chip. Known methods of measuring signal skew between two on-chip signals involves measuring differences in pad to pad delays on a chip by stimulating a bypass path and a real path using a tester that is external to the chip. The difference between the signal sent along the bypass path and the signal sent along the real path represents a signal skew. The signal skew may be a measure, for example, of delay due to components along the real path.
The problems with this approach to determining signal skew are that an external tester must use two channels to perform the measurements of the signal skew, one for stimulation of the pad leading to the bypass path or the real path, and another channel to measure the received signals at the output pad. Each channel introduces a significant source of error in the measurement of the signal skew.
In addition, the components on the chip are typically able to handle signals at a much higher speed than the speed at which the external testers can drive signals onto the chip for testing. Thus, the external testers do not provide a completely accurate representation of the full capability of the chip. This leads to errors in verifying simulation data. Thus, it would be beneficial to have an apparatus and method for measuring signal skew that avoids the problems noted above with known methods.
SUMMARY OF THE INVENTION
The present invention provides an on-chip apparatus and method for measuring signal skew between two on-chip signals. The apparatus and method of the present invention generates a pulse train which is at a first state during a time period between a clocking of a circuit component and a time at which the circuit component generates an output signal, and a second state between clockings of the circuit component. The pulse width of the pulses in the pulse train is representative of the skew, i.e. change of phases or timing, in the signal due to the presence of the component. The pulse train may further be pseudo-clock divided to generate more measurable pulses. The output from the present invention is produced using a single output pad.
The apparatus and method produce a long measurable pulse width on a single output pad. With the present invention, a pulse width of 10 s of ns is achievable instead of 1-2 ns as in the known art. The pulse width measurement is done with a single tester channel instead of two as in the known art. The hard macro approach of the present invention minimizes any error from layout proximity and routing issues.
These and other features and advantages of the present invention will be described in, or will become apparent to those of ordinary skill in the art in view of, the following detailed description of the preferred embodiments.
REFERENCES:
patent: 5333154 (1994-07-01), Hengeveld et al.
patent: 6069508 (2000-05-01), Takai
patent: 6173432 (2001-01-01), Harrison
patent: 6337832 (2002-01-01), Ooishi et al.
Carstens Yee & Cahoon, L.L.P.
Dinh Paul
LSI Logic Corporation
Smith Matthew
LandOfFree
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