Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1997-12-16
2002-04-02
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S118000, C711S154000, C365S220000, C365S221000, C365S230010
Reexamination Certificate
active
06366979
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to FIFOs generally, and more particularly, to a high speed FIFO retransmit method and apparatus.
BACKGROUND OF THE INVENTION
First-in First-out (FIFO) buffers may use retransmit schemes to allow a user to return to the first location in the FIFO and re-read data. When a retransmit is asserted, the read pointer returns to the first location. For proper operation of the retransmit, the write pointer should not pass the first location.
Certain known constraints hinder the ability of the retransmit function to have a quick recovery time. Look ahead architectures may be implemented in high performance FIFOs to allow the read pointer to look ahead of its current location so that the information may be accessed faster during a read from the FIFO. A retransmit scheme may interrupt the look ahead architecture due to precharging requirements of the bitlines. Data corruption due to charge sharing on the bitlines may occur without the proper precharge time. To avoid data corruption due to charge sharing, the bitlines of the FIFO should be precharged before the read wordlines are asserted. The FIFO must then initiate a bitline precharged cycle upon the assertion of a retransmit. The more words there are in the memory array, the longer the precharge cycle time. For large memory arrays, the long precharge cycle creates an unacceptably long retransmit recovery time.
Referring to
FIG. 1
, a circuit
10
is shown illustrating a previous retransmit system implemented with registers to store data for retransmit. The circuit
10
generally comprises a write in register
12
, a retransmit lower register
14
, a retransmit upper register
16
, a holding register
18
, a read out register
20
and a read hold register
22
. A write data signal is received at an input
24
of the write in register
12
. The write data signal is also presented to a bus
26
. The bus
26
presents an output
28
representing the read data. The write in register
12
has an output
30
that presents a signal to a bus
32
as well as to an input
34
of the write hold register
18
. The bus
32
generally presents a signal to the bus
26
. The register
14
is connected through a bus
36
to the bus
32
. Similarly, the registers
16
are connected through a bus
38
to the bus
32
. The write hold register
18
has an output
40
that presents a signal to the bus
32
. The read out register
20
presents a signal on an output
42
to the bus
32
. The read out register
20
has an input
44
that receives a signal from the read hold register
22
. The read hold register
22
has an input
46
that receives a signal from the memory array. The write hold register
18
also has an output
48
that presents a signal to the memory array. The retransmit lower register
14
and the retransmit upper register
16
store the information when the initial words are read from the memory array. After a retransmit, data is read from the registers
14
and
16
. However, the bitlines must first be precharged before reading, which may interrupt the look ahead architecture. While the registers accommodate the precharge, they generally require complex logic and consume a large amount of area on the chip.
The write in register
12
, the retransmit lower register
14
, the retransmit upper register
16
, the write hold register
18
, the read out register
20
and the read hold register
22
may be generally implemented as 32-bit registers, as shown in FIG.
1
. While the circuit
10
may provide the appropriate retransmit scheme, it becomes cumbersome to create such numerous wide bit registers.
SUMMARY OF THE INVENTION
The present invention concerns a circuit and method comprising a memory array, a cache memory and a logic circuit. The memory array may include a read pointer, a write pointer and a plurality of rows. The cache memory may be configured to store one or more bits. The logic circuit may be configured to control the output of the circuit by presenting either (i) an output from the memory array or (ii) an output from the cache memory.
The objects, features and advantages of the present invention include providing an architecture that allows for short retransmit recovery times by implementing a read cache in a FIFO device. The present invention allows an incremental granularity of a retransmit cache by implementing the cache in “word” increments, provides scaleability to allow more cache to be added as recovery time requirements increase, and provides a logic implementation that may be independent of the technology, memory cell and data path architecture implemented on the specific cell.
REFERENCES:
patent: 5317720 (1994-05-01), Stamm et al.
patent: 5319766 (1994-06-01), Thaller et al.
patent: 5388247 (1995-02-01), Goodwin et al.
patent: 5461718 (1995-10-01), Tatosian et al.
patent: 5901100 (1999-05-01), Taylor
Pidugu L. Narayana et al., U.S.S.N. 08/768,407, now patent 5860160 High Speed FIFO and Retransmit Scheme, filed Dec. 18, 1996.
Cress Daniel Eric
Narayana Pidugu L.
Wu Ping
Christopher P. Maiorana P.C.
Cypress Semiconductor Corp.
Thai Tuan V.
LandOfFree
Apparatus and method for shorting retransmit recovery times... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and method for shorting retransmit recovery times..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for shorting retransmit recovery times... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2878237