Apparatus and method for sharing a branch prediction unit in a m

Details Apparatus and method for sharing a branch prediction unit in a m Apparatus and method for sharing a branch prediction unit in a m

1997-06-30

2000-02-01

Lim, Krisna

Electrical computers and digital processing systems: processing

Processing control

Branching

712235, 712 23, G06F 938

Patent

active

060214899

ABSTRACT:
A microprocessor that includes first and second Instruction Fetch Units (IFU) coupled therebetween is provided. The first IFU implements a first Instruction Set Architecture (ISA). The second IFU implements a second ISA. The microprocessor further includes a shared branch prediction unit coupled to the first and second IFU. The shared branch prediction unit stores prediction-related information. In the same paragraph, the present invention also provides a method of performing branch prediction. According to this method, an instruction pointer is provided to a branch prediction unit that stores information shared by first and second IFU. The instruction pointer is generated by one of the first and second IFU that is active. Determination is made of whether an instruction corresponding to the instruction pointer, provided to the branch prediction unit, is a branch instruction, and if so, it is determined if a branch is predicted taken. If the branch instruction is predicted taken, target address corresponding to the branch instruction is provided to the first and second IFU.

REFERENCES:
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patent: 5606676 (1997-02-01), Grochowski et al.
patent: 5655098 (1997-08-01), Witt et al.
patent: 5742805 (1998-04-01), Kulkarni et al.
patent: 5794028 (1998-08-01), Tran
patent: 5822574 (1998-10-01), Tran

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