Apparatus and method for serialized set prediction

Details Apparatus and method for serialized set prediction Apparatus and method for serialized set prediction

1996-06-26

1999-09-14

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Address formation

Address mapping

711136, 711140, 711147, 711213, G06F 1212

Patent

active

059537477

ABSTRACT:
A prediction mechanism for improving direct-mapped cache performance is shown to include a direct-mapped cache, partitioned into a plurality of pseudo-banks. Prediction means are employed to provide a prediction index which is appended to the cache index to provide the entire address for addressing the direct mapped cache. One embodiment of the prediction means includes a prediction cache which is advantageously larger than the pseudo-banks of the direct-mapped cache and is used to store the prediction index for each cache location. A second embodiment includes a plurality of partial tag stores, each including a predetermined number of tag bits for the data in each bank. A comparison of the tags generates a match in one of the plurality of tag stores, and is used in turn to generate a prediction index. A third embodiment for use with a direct mapped cache divided into two partitions includes a distinguishing bit ram, which is used to provide the bit number of any bit which differs between the tags at the same location in the different banks. The bit number is used in conjunction with a complement signal to provide the prediction index for addressing the direct-mapped cache.

REFERENCES:
patent: 4894772 (1990-01-01), Langendorf
patent: 4942520 (1990-07-01), Langendorf
patent: 5235697 (1993-08-01), Steely et al.
patent: 5283873 (1994-02-01), Steely et al.
patent: 5509135 (1996-04-01), Steely, Jr.
Kessler, R. E. et al., "Inexpensive Implementations of Set-Associativity", Computer Architecture News, vol. 17, No. 3, Jun. 1989, pp. 131-139.

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