Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2007-10-31
2009-02-17
Hur, J. H. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S210100, C365S230040, C365S189070
Reexamination Certificate
active
07492658
ABSTRACT:
A dynamic random access memory (DRAM) having DRAM cells coupled to wordlines and bitlines. In a self-refresh mode, the cells coupled with the even numbered rows retain main data previously stored therein and the assistant data, which is logically opposite to the main data, is overwritten into the cells coupled with the wordlines of the odd numbered rows. When the DRAM enters the self-refresh mode, a starting refresh address for the self-refresh mode is detected. If the detected starting refresh address does not match with a predetermined correct address set for the self-refresh operation mode, a dummy refresh cycle will be established in an entry-burst self-refresh period. During the dummy refresh cycle, a dummy refresh command is added to increment an internal row address counter that provides row addresses for self-refreshing the cells of the selected wordlines within the cell array.
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Borden Ladner Gervais LLP
Hung Shin
Hur J. H.
Mosaid Technologies Incorporated
Yang Han
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