Apparatus and method for selectively invalidating entries in...

Details Apparatus and method for selectively invalidating entries in... Apparatus and method for selectively invalidating entries in...

2008-06-17

2008-06-17

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

C711S100000, C711S133000, C711S154000, C711S205000, C711S206000, C711S207000

Reexamination Certificate

active

07389400

ABSTRACT:
An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may be set according to the addressing mode used to create the cache entry. One or more “hint bits” are defined in an instruction that allow specifying which of the entries in the address translation cache are selectively preserved during an invalidation operation according to the value(s) of the translation mode bit(s). In the alternative, multiple instructions may be defined to preserve entries in the address translation cache that have specified addressing modes. In this manner, more intelligence is used to recognize that some entries in the address translation cache may be valid after a task or partition switch, and may therefore be retained, while other entries in the address translation cache are invalidated.

REFERENCES:
patent: 6338128 (2002-01-01), Chang et al.
patent: 2005/0182913 (2005-08-01), DeMent et al.

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