Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral configuration
Reexamination Certificate
1999-05-24
2002-06-04
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral configuration
C710S005000, C710S058000, C710S120000, C709S209000
Reexamination Certificate
active
06401142
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to data transfer and more particularly, to methods and systems for transferring data between a buffer memory and a host bus.
2. Background Art
Network interface devices are commonly used to transmit data between a host computer and network communication systems, such as a local area network. Typical network interface devices include Ethernet-type and IEEE 802.3. One primary function of a network interface is to control the transfer of data between a buffer and the host bus.
The data stored in the buffer is retrieved as a result of one of two types of requests, namely master and slave. Generally in master mode, a transfer is initiated by a master device, which must arbitrate for use of the host bus with a host CPU prior to retrieving the data. In slave mode, the host CPU controls access of the buffer and retrieval of data. A slave access can be performed using two different types of mapping: memory mapping and Input/Output (I/O) mapping.
Traditionally, transfer of data between the buffer memory and the host bus has been accomplished by providing specific logic for each type of request.
FIG. 8
is a block diagram illustrating a typical buffer architecture
200
for accessing data from buffer memory. An interface unit
202
receives master and slave requests to access the buffer memory
204
. The request is directed to a transfer logic
206
that transfers data to or from the buffer memory
204
. The transfer logic
206
must be capable of handling each type of request individually. Thus, the interface unit
202
transfers the request to a specific logic portion in the transfer logic
206
based on the nature of the request. For example, the transfer logic
206
includes a first logic circuit
208
that services a master request, a second logic circuit
210
that services an I/O mapped slave request, and a third logic circuit
212
that services memory mapped slave requests. Furthermore, after a data transfer mode has been determined according to the request, the mode cannot be changed during the transmission of the frame.
In a conventional system, once a data transfer has been initiated, the mode of transfer (e.g., master, slave I/O mapped, slave memory mapped) cannot be altered within the transmission of a data frame. That is, a master transfer request triggers a data transfer in master transfer mode in which data transmission proceeds in this mode until complete transfer of the frame or termination of the session occurs.
Hence, a primary disadvantage associated with current methods of transferring data is that the mode of transfer can not be changed during data transmission to adapt to the needs of the application (e.g., protocols, drivers) or to changes in the availability of computing resources. Another disadvantage is the excessive amount of logic necessary to service the different types of requests. Yet another disadvantage is the increased latency encountered during the data transfer process. This latency can be defined as the delay between the time when data is available in the buffer to the time it is delivered to the host bus. Additional delays are encountered during transfers initiated by a master device, because, as previously mentioned, the master device must arbitrate for access to the bus with other master devices that also require use of the bus.
DISCLOSURE OF THE INVENTION
There is a need for an arrangement for supplying data frames to a host bus that is capable of changing the type of data transfer mode within the transmission of a data frame.
There is also a need for an arrangement for supplying data frames to a host bus that minimizes the logic necessary to access a buffer memory using different types of requests.
There is also a need for an arrangement for supplying data frames to a host bus that minimizes the latency encountered during the transfer of data from a buffer memory.
These and other needs are attained by the present invention, where master and slave accesses to the buffer are serviced by a single logic circuit that permits the data transfer modes to be changeable, eliminates the need for arbitration, and reduces the amount of latency encountered during the data transfer process.
In accordance with one aspect of the present invention, a network interface for supplying data frames to and from a host bus comprises a buffer memory for storing a data frame. A bus interface unit is configured for outputting the data frames onto the host bus according to a master transfer mode and a slave transfer mode. Request logic generates a generic request to access the buffer memory in response to receipt of either a master transfer request or a slave transfer request. A memory management unit is configured for transferring the data frame between the buffer memory and the host bus in response to the generic request. The master transfer mode is changeable to the slave transfer mode and vice versa during the outputting of a data frame onto the host bus. Hence, the network interface can alternately transfer data in a master transfer mode or a slave transfer mode and vice versa within a single frame, thereby permitting flexibility in the allocation of computing resources and optimizing the performance of applications.
Another aspect of the present invention provides a network interface device for storing frame data. A request logic unit is configured for generating a generic request to access the buffer memory in response to receipt of either a detected master transfer request or a slave transfer request. A bus side control logic unit is configured for determining a mode of data transfer based upon detection of the master transfer request or a slave transfer request; the mode is a master transfer mode if the master transfer request is received or a slave transfer mode if the slave transfer request is received. A memory management unit is configured for transferring the stored frame data from the buffer memory in response to the generic request to the host bus. The mode of data transfer is changeable during the transfer of the stored frame data. Under this arrangement, efficiency of computing resource usage can be realized with the ability to change data transfer mode within the transfer of frame data within a single data frame.
Yet another aspect of the invention provides a method for transferring a data frame between a buffer memory and a host bus. The method comprises receiving a master transfer request or a slave transfer request wherein the master transfer request indicates a master transfer mode and the slave transfer request indicates a slave transfer mode, changing the master transfer mode to the slave transfer mode and vice versa, generating a generic request in response to the receiving step, and transferring the data frame between the buffer memory and the host bus in response to the generic request. Therefore, the modes of data transfer can be readily changed from master to slave (I/O mapped or memory mapped) and vice versa to accommodate requirements of the applications.
Additional advantages, and novel features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
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Niu Autumn Jane
Williams Robert Alan
Advanced Micro Devices , Inc.
Gaffin Jeffrey
Mai Rijue
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