Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
1999-11-24
2001-05-15
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Floating gate
Multiple values
C365S189020, C365S230020
Reexamination Certificate
active
06233173
ABSTRACT:
TECHNICAL FIELD
The invention pertains to multistate memory systems and to methods and circuits for selecting bits that have been read from memory cells of such systems. More specifically, the invention is a method and system (and a circuit for use in such system) for sequentially selecting subsets of a set of data bits read in parallel from an array of flash memory cells (or other memory cells) operated as multistate memory devices, and sequentially asserting the selected subsets to a data bus.
BACKGROUND OF THE INVENTION
In conventional single-bit-per-cell memory systems (binary memory systems), each memory cell assumes one of two information storage states: either an “on” state or an “off” state. The state of each cell (“on” or “off”) defines one binary bit of information. As a result, a binary memory system capable of storing N bits of binary data requires N separate memory cells.
Increasing the number of bits which can be stored using a binary memory system depends upon increasing the number of memory cells on a one-for-one basis with the number of bits of data to be stored. Methods for increasing the number of memory bits stored in a binary memory system have relied upon techniques such as manufacturing larger dies which contain more memory cells, or using improved photolithography techniques to build smaller memory cells. Reducing the size of a memory cell allows more cells to be placed on a given area of a single die.
An alternative to a binary memory system (which stores one binary bit per memory cell) is a multistate memory device which stores two or more binary bits of data in a single memory cell.
One type of memory device includes an array of electrically erasable and programmable devices known as flash memory cells. Each of such cells can be operated either as a binary memory device (storing one binary bit) or as a multistate memory device. To program a flash memory cell, appropriate voltages are applied to the source, drain, and control gate of the transistor which comprises the cell for an appropriate time period. This causes electrons to tunnel or be injected from a channel region to a floating gate. The amount of charge residing on the floating gate determines the voltage required on the control gate in order to cause the cell to conduct a particular level of current between the source and drain. This voltage is termed the threshold voltage, V
th
, of the cell.
When a flash memory cell is operated as a binary memory device, the cell is programmed or erased to have a selected one of two different threshold voltages (the cell is either erased so as to have a first threshold voltage or it is programmed so as to have a second threshold voltage). The cell is then read by measuring whether the current between its source and drain (or a voltage related to such current) exceeds a threshold amount (for a known set of voltages applied to its source, control gate, and drain). Measurement of current having at least a first magnitude (a “first” current) between the source and drain regions determines an “on” or erased state of the cell (corresponding to a logic value of one). An “off” or programmed state of the cell (corresponding to a logic value of zero) is determined by a measured current less than the first current between the source and drain regions. For a given threshold voltage of a cell, the cell can be made to conduct or not conduct current (i.e., current greater than or equal to the first current) by applying a given set of voltages thereto. The cell conducts when a voltage applied to its control gate (with reference to its source voltage) is greater than the threshold voltage. By measuring whether a cell conducts current (i.e., current greater than or equal to the first current) at a given set of applied voltages, the state of the cell (programmed or if erased) is measured. Typically, such a measurement is made using a sense amplifier (as described below).
When a flash memory cell is operated as a multistate memory device, the cell is programmed or erased to cause it to have a selected one of three or more different threshold voltages. In other words, the cell is either erased (so as to have a first threshold voltage), or it is programmed into one of at least two programmed states (so as to have a second threshold voltage in one programmed state, or a third threshold voltage in another programmed state, or a fourth threshold voltage in a third one of the programmed states, and so on). Each distinct threshold voltage corresponds to a set of at least two binary data bits in the following sense. Application of a voltage less than a first threshold voltage to the cell's control gate causes conduction of less than a first current between the source and drain regions (corresponding to a first set of binary bits, e.g., “00” or “000”), application of a voltage greater than the first threshold voltage but less than a second threshold voltage to the cell's control gate causes conduction of more than the first current but less than a second current between the source and drain regions (corresponding to a second set of binary bits, e.g., “01” or “001”), application of a voltage greater than the second threshold voltage but less than a third threshold voltage to the cell's control gate causes conduction of more than the second current but less than a third current between the source and drain (corresponding to a third set of binary bits, e.g., “10” or “010”), application of a voltage greater than the third threshold voltage to the cell's control gate causes conduction of more than the third current between the source and drain (corresponding to a fourth set of binary bits, e.g., “11” or “011”), and so on. This effectively allows multiple bits of binary data to be stored within a single memory cell.
When reading the state of a memory cell (operated as a multistate memory device), a binary decoded value (an ordered set of two or more binary bits indicative of the data stored in the cell) is generated which corresponds to a measured current between the cell's source and drain (or a measured voltage related to such current). Typically, the voltage related to the source-to-drain current is measured using sense amplifier circuitry to which a set of preselected reference voltage values (each corresponding to one of the threshold voltages) are applied, in a manner to be explained with reference to
FIG. 3
below.
Memory system
3
shown in
FIG. 1
includes an array
16
of nonvolatile memory cells (which can be flash memory cells), and is an example of a memory system which can be operated as a multistate memory system. Memory system
3
is implemented as an integrated circuit. Memory cell array
16
comprises rows and columns of memory cells (each row of cells connected along a different wordline, and each column of cells connected along a different bitline). Memory chip
3
also includes row decoder circuit (X address decoder)
12
and column multiplexer circuit (Y multiplexer)
14
connected to array
16
.
Wordlines of array
16
are conveniently referred to as being numbered consecutively from top to bottom of array
16
, so that the wordlines are: wordline
0
(or “WL0”), wordline
1
(or “WL1”), wordline
2
, wordline n-1, and wordline n (where n is an integer)
FIG. 2
is a schematic diagram of an implementation of memory array
16
of
FIG. 1
from which data can be read in accordance with the present invention. The
FIG. 2
implementation of array
16
includes flash memory cells arranged in rows and columns. Each cell is implemented by a floating-gate N-channel transistor (e.g., transistors N
1
, N
3
, and Nn connected along bitline
13
), as shown schematically. All the cells in a particular column have their drain regions connected to a common bitline (e.g., bitline
13
or bitline
15
) and all the cells in a particular row have their control gates connected to a common wordline (one of wordlines WL0, WL1, . . . , WLn). The source region (S) of each of the cells is connected to a common source line SL. Alternatively, it is possible to arrange
Chevallier Christophe J.
Lakhani Vinod C.
Dinh Son T.
Micro)n Technology, Inc.
Nguyen Hien
Schwegman Lundberg Woessner & Kluth P.A.
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