Apparatus and method for selecting and buffering inputs of progr

Details Apparatus and method for selecting and buffering inputs of progr Apparatus and method for selecting and buffering inputs of progr

1995-04-10

1996-06-04

Westin, Edward P.

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 41, 326 44, 327408, H03K 19177

Patent

active

055237053

ABSTRACT:
A programmable logic circuit having a routing matrix capable of providing 100% connectability and routability of a plurality of input signals to their appropriate configuration function blocks. In the present invention, input signals are first routed through the routing matrix before being processed by the input buffers. Thus, a slow user signal is processed by the relatively slow routing matrix before being provided with increased drive by the input buffers and passed on to the faster logical blocks. A number of programmable control bits are stored in SRAM. These control bits are decoded to determine which of the transmission gates of the routing matrix should be enabled. In this manner the input signal is routed to the appropriate configuration function block. Following the routing matrix is the input buffer. The highly driven output signal from the buffer is then passed to the configuration function block which performs the programmed logic functions on the signal.

REFERENCES:
patent: 4706216 (1987-11-01), Carter
patent: 4772811 (1988-09-01), Fujioka et al.
patent: 4847612 (1989-07-01), Kaplinsky
patent: 4963768 (1990-10-01), Agrawal et al.
patent: 5221865 (1993-06-01), Phillips et al.
patent: 5243599 (1993-09-01), Barrett et al.

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