Apparatus and method for secure hash algorithm

Electrical computers and digital processing systems: support – Data processing protection using cryptography – Computer instruction/address encryption

Reexamination Certificate

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Details

C713S181000, C380S037000, C712S032000, C712S041000, C712S208000

Reexamination Certificate

active

07921300

ABSTRACT:
An x86-compatible microprocessor that executes an application program fetched from memory, including a single, atomic hash instruction directing the x86-compatible microprocessor to perform the hash operation. The single, atomic hash instruction has an opcode field and a repeat prefix field. The opcode field prescribes that the x86-compatible microprocessor accomplish the hash operation. The repeat prefix field is coupled to the opcode field and indicates that the hash operation prescribed by the single, atomic hash instruction is to be accomplished on one or more message blocks. The x86-compatible microprocessor has a hash unit that is configured to execute a plurality of hash computations on each of the one or more message blocks to generate a corresponding intermediate hash value, where a last intermediate hash value that is computed for a last message block after processing all previous message blocks includes a message digest corresponding to the one or more message blocks.

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