Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-12-11
2007-12-11
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C703S016000
Reexamination Certificate
active
10642084
ABSTRACT:
The present invention is directed to reducing errors due to floating values introduced during tristate and contention when modeling a register in RTL. In one embodiment, the floating values are replaced by predetermined desired values corresponding to the floating values which are both stored in a lookup table. In another embodiment, when a floating value is detected, that value is ignored and the previous clock value is retained.
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Chang Tzung-Chin
Dupenloup Guy
Gunawan Wira
Nguyen Khai
Rangan Gopinath
Altera Corporation
Cho L.
Levin Naum B.
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