Apparatus and method for RTL based full chip modeling of a...

Details Apparatus and method for RTL based full chip modeling of a... Apparatus and method for RTL based full chip modeling of a...

2007-02-13

2007-02-13

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

10821466

ABSTRACT:
An RTL representation for a LAB is generated. A full chip RTL model is then generated using a plurality of the LAB RTLs. Using the full chip RTL model, a full chip simulation of the PLD chip is performed to verify and debug the electronic design.

REFERENCES:
patent: 5911061 (1999-06-01), Tochio et al.
patent: 6651225 (2003-11-01), Lin et al.
patent: 2004/0268288 (2004-12-01), Bajuk et al.

Affiliated with

Also associated with

Rating

Apparatus and method for RTL based full chip modeling of a... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Apparatus and method for RTL based full chip modeling of a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for RTL based full chip modeling of a... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3889493