Apparatus and method for responding to data retention loss...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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C714S758000, C714S049000, C714S785000, C714S799000, C714S710000, C714S718000

Reexamination Certificate

active

07496822

ABSTRACT:
In a non-volatile memory unit such as a flash memory unit, the degradation of charge can result in an error during a read operation. By using the error checking and correction techniques, a determination can be made whether a detected error can be corrected and, if correctable, is the consistent with charge degradation at that bit position displaying the error. When a correctable error is detected, the signal group address and the correction pattern are stored and an interrupt request flag applied to the central processing unit. When the interrupt flag is processed, the central processing unit, using the signal group address and the correction pattern, restores the charge of the bit position in the memory unit. In this manner, further read operations involving the restored bit position will not repeat the corrected error.

REFERENCES:
patent: 5490155 (1996-02-01), Abdoo et al.
patent: 5978953 (1999-11-01), Olarig
patent: 6272651 (2001-08-01), Chin et al.
patent: 6359806 (2002-03-01), Nozoe et al.
patent: 6505305 (2003-01-01), Olarig

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