Apparatus and method for resetting a dynamic logic circuit

Details Apparatus and method for resetting a dynamic logic circuit Apparatus and method for resetting a dynamic logic circuit

1997-06-26

1999-11-16

Tokar, Michael

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326 98, 326 83, H03K 19096, H03K 19094

Patent

active

059864753

ABSTRACT:
An apparatus and method for resetting a dynamic logic circuit is disclosed. The apparatus includes an input circuit coupled to a plurality of input nodes wherein the input circuit comprises a plurality of FETs connected between a first voltage node and a dynamic node of a logic circuit. The gate electrode of each input circuit FET is connected to one of the input nodes. Precharged FET is connected between the dynamic node and a second voltage node. The precharge FET is configured to conduct a current for precharging the dynamic node to a predetermined voltage. An inverter is coupled between the dynamic node and an output node. A precharge control circuit is connected in a feedback path between the output node and the precharge FET. The precharge control signal activates the precharge control FET in response to a RESET pulse width and deactivates the precharge FET in response to the voltage on the dynamic node. As such, the precharge FET is controlled and the dynamic node is properly precharged independent of the RESET pulse width.

REFERENCES:
patent: 5550490 (1996-08-01), Durham et al.
patent: 5818264 (1998-10-01), Ciraula et al.
patent: 5828243 (1998-10-01), Sprague
patent: 5831452 (1998-11-01), Nowak et al.
patent: 5838169 (1998-11-01), Schorn

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