Apparatus and method for reset distribution

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000

Reexamination Certificate

active

11351425

ABSTRACT:
A skew-tolerant, glitch-free reset distribution apparatus and method are provided in an intellectual property (IP) block that supports a multi-channel input/output protocol. During reset mode, synchronizers are used to create more predictable timing, to pipeline the propagation delay, and to tolerate RC-induced skews of up to a clock period in routing a reset signal to all the channels and within the channels in an IP block. Two control signals, which are available from programmable logic resource core circuitry, are used to control the input of the reset signal into the IP block. Because the control signals are designed to be glitch-free, the reset signal is therefore also glitch-free, thus preventing the IP block from inadvertently transitioning into or out of reset mode.

REFERENCES:
patent: 4059842 (1977-11-01), Meacham
patent: 4983857 (1991-01-01), Steele
patent: 5379302 (1995-01-01), Andrews
patent: 5652529 (1997-07-01), Gould et al.
patent: 6580776 (2003-06-01), Chang et al.
patent: 6650140 (2003-11-01), Lee et al.
patent: 2001/0033188 (2001-10-01), Aung et al.
U.S. Appl. No. 10/059,014, filed Jan. 29, 2002, Lee et al.

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