Apparatus and method for reporting program halts in an...

Details Apparatus and method for reporting program halts in an... Apparatus and method for reporting program halts in an...

2003-12-05

2008-07-22

Wilson, Yolanda L. (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S034000, C712S227000, C717S124000

Reexamination Certificate

active

07404106

ABSTRACT:
In a target processor having a non-protected pipeline, the execution code is typically provided with interruptible code portions and with non-interruptible code portions. The non-interruptible code portions prevent implementation of a real time interrupt that would corrupt the code so that execution could not be resumed. A storage unit is provided that stores a signal permitting a code execution halt even during a non-interruptible code portion. In this manner, a program developer can determine the status of the processor at any point in the code execution. When the execution halt is initiated during a non-interruptible code segment, a bit is set in a bit position of a memory-mapped register. This bit position can be transferred from the target processor to the host processing unit during a transfer of status data.

REFERENCES:
patent: 5970241 (1999-10-01), Deao et al.
patent: 6112298 (2000-08-01), Deao et al.
patent: 6598150 (2003-07-01), Williams et al.
patent: 6981178 (2005-12-01), Nardini et al.

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